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11. 发明授权

US06677200B2 Method of forming non-volatile memory having floating trap type device 失效
标题翻译：形成具有浮动陷阱型装置的非易失性存储器的方法
公开(公告)号：US06677200B2
公开(公告)日：2004-01-13
申请号：US10194182
申请日：2002-07-12
申请人： Chang-Hyun Lee , Jung-Dal Choi , Sung-Hoi Hur
发明人： Chang-Hyun Lee , Jung-Dal Choi , Sung-Hoi Hur
IPC分类号： H01L213366
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/66833 , Y10S438/954
摘要： A method of forming a non-volatile memory having a floating trap-type device is disclosed in the present invention. In the method, a relatively thick thermal oxide layer is formed at a semiconductor substrate and patterned to leave a thick thermal oxide pattern at a high-voltage region (a high-voltage region defining step). An oxide-nitride-oxide (ONO) layer is formed over substantially the entire surface (the substantial surface) of the semiconductor substrate and patterned to leave an ONO pattern at a cell memory region (a cell memory region defining step). After the high-voltage region defining step and the cell memory region defining step, a thermal oxidizing process is performed with respect to the semiconductor substrate where a low-voltage region is exposed, thereby forming a relatively thin gate insulation layer for a low-voltage type device (a low-voltage region defining region).
摘要翻译：在本发明中公开了形成具有浮动陷阱型装置的非易失性存储器的方法。在该方法中，在半导体衬底上形成相对较厚的热氧化物层，并将其图案化以在高电压区域（高电压区域限定步骤）处留下厚的热氧化物图案。在半导体衬底的基本上整个表面（基本表面）上形成氧化物 - 氧化物（ONO）层，并将其图案化以在单元存储区（单元存储区定义步骤）处留下ONO图案。在高电压区域定义步骤和电池存储区域限定步骤之后，对于暴露低电压区域的半导体衬底进行热氧化处理，从而形成用于低电压的较薄的栅极绝缘层（低电压区域限定区域）。

12. 发明授权

US07259421B2 Non-volatile memory devices having trenches 失效
标题翻译：具有沟槽的非易失性存储器件
公开(公告)号：US07259421B2
公开(公告)日：2007-08-21
申请号：US11020920
申请日：2004-12-23
申请人： Sung-Hoi Hur , Jung-Dal Choi
发明人： Sung-Hoi Hur , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the substrate between the first gate pattern and the second gate pattern such that the split source/drain region is divided by the trench. The split source/drain region includes a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench and spaced apart from the first source/drain subregion. A connecting region is formed in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion. Related methods are also discussed.
摘要翻译：半导体存储器件包括其中具有沟槽的半导体衬底。第一和第二栅极图案形成在与沟槽相邻的衬底的表面上，其相应的一个位于沟槽的相应的相对侧上。在第一栅极图案和第二栅极图案之间的衬底中形成分离源极/漏极区域，使得分离源极/漏极区域被沟槽分开。分离源极/漏极区域包括在第一栅极图案和沟槽之间的第一源极/漏极子区域和在第二栅极图案和沟槽之间并与第一源极/漏极子区域间隔开的第二源极/漏极子区域。在从第一源/漏区域到第二源极/漏极子区域的沟槽周围延伸的衬底中形成连接区域。还讨论了相关方法。

13. 发明申请

US20060027855A1 Non-volatile memory devices having trenches and methods of forming the same 失效
标题翻译：具有沟槽的非易失性存储器件及其形成方法
公开(公告)号：US20060027855A1
公开(公告)日：2006-02-09
申请号：US11020920
申请日：2004-12-23
申请人： Sung-Hoi Hur , Jung-Dal Choi
发明人： Sung-Hoi Hur , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the substrate between the first gate pattern and the second gate pattern such that the split source/drain region is divided by the trench. The split source/drain region includes a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench and spaced apart from the first source/drain subregion. A connecting region is formed in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion. Related methods are also discussed.
摘要翻译：半导体存储器件包括其中具有沟槽的半导体衬底。第一和第二栅极图案形成在与沟槽相邻的衬底的表面上，其相应的一个位于沟槽的相应的相对侧上。在第一栅极图案和第二栅极图案之间的衬底中形成分离源极/漏极区域，使得分离源极/漏极区域被沟槽分开。分离源极/漏极区域包括在第一栅极图案和沟槽之间的第一源极/漏极子区域和在第二栅极图案和沟槽之间并与第一源极/漏极子区域间隔开的第二源极/漏极子区域。在从第一源/漏区域到第二源极/漏极子区域的沟槽周围延伸的衬底中形成连接区域。还讨论了相关方法。

14. 发明申请

US20070066003A1 METHODS OF FORMING NON-VOLATILE MEMORY DEVICES HAVING TRENCHES 失效
标题翻译：形成具有斜面的非易失性存储器件的方法
公开(公告)号：US20070066003A1
公开(公告)日：2007-03-22
申请号：US11558634
申请日：2006-11-10
申请人： Sung-Hoi Hur , Jung-Dal Choi
发明人： Sung-Hoi Hur , Jung-Dal Choi
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the substrate between the first gate pattern and the second gate pattern such that the split source/drain region is divided by the trench. The split source/drain region includes a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench and spaced apart from the first source/drain subregion. A connecting region is formed in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion. Related methods are also discussed.
摘要翻译：半导体存储器件包括其中具有沟槽的半导体衬底。第一和第二栅极图案形成在与沟槽相邻的衬底的表面上，其相应的一个位于沟槽的相应的相对侧上。在第一栅极图案和第二栅极图案之间的衬底中形成分离源极/漏极区域，使得分离源极/漏极区域被沟槽分开。分离源极/漏极区域包括在第一栅极图案和沟槽之间的第一源极/漏极子区域和在第二栅极图案和沟槽之间并与第一源极/漏极子区域间隔开的第二源极/漏极子区域。在从第一源/漏区域到第二源极/漏极子区域的沟槽周围延伸的衬底中形成连接区域。还讨论了相关方法。

15. 发明授权

US07501322B2 Methods of forming non-volatile memory devices having trenches 失效
标题翻译：形成具有沟槽的非易失性存储器件的方法
公开(公告)号：US07501322B2
公开(公告)日：2009-03-10
申请号：US11558634
申请日：2006-11-10
申请人： Sung-Hoi Hur , Jung-Dal Choi
发明人： Sung-Hoi Hur , Jung-Dal Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the substrate between the first gate pattern and the second gate pattern such that the split source/drain region is divided by the trench. The split source/drain region includes a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench and spaced apart from the first source/drain subregion. A connecting region is formed in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion. Related methods are also discussed.
摘要翻译：半导体存储器件包括其中具有沟槽的半导体衬底。第一和第二栅极图案形成在与沟槽相邻的衬底的表面上，其相应的一个位于沟槽的相应的相对侧上。在第一栅极图案和第二栅极图案之间的衬底中形成分离源极/漏极区域，使得分离源极/漏极区域被沟槽分开。分离源极/漏极区域包括在第一栅极图案和沟槽之间的第一源极/漏极子区域和在第二栅极图案和沟槽之间并与第一源极/漏极子区域间隔开的第二源极/漏极子区域。在从第一源/漏区域到第二源极/漏极子区域的沟槽周围延伸的衬底中形成连接区域。还讨论了相关方法。

16. 发明申请

US20060124988A1 Methods of fabricating flash memory devices having self-aligned floating gate electrodes and related devices 审中-公开
标题翻译：制造具有自对准浮栅的闪存器件和相关器件的方法
公开(公告)号：US20060124988A1
公开(公告)日：2006-06-15
申请号：US11291142
申请日：2005-11-30
申请人： Sung-Hoi Hur , Jung-Dal Choi , Kyeong-Tae Kim , Jong-Ho Park , Jae-Duk Lee , Ki-Nam Kim
发明人： Sung-Hoi Hur , Jung-Dal Choi , Kyeong-Tae Kim , Jong-Ho Park , Jae-Duk Lee , Ki-Nam Kim
IPC分类号： H01L21/82 , H01L21/8238
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor memory device is fabricated by forming an active region protruding from a semiconductor substrate, forming an isolation layer on the substrate adjacent opposing sidewalls of the active region, and forming a floating gate electrode on a surface of the active region between the opposing sidewalls thereof. The floating gate electrode is formed to extend beyond edges of the surface of the active region onto the isolation layer. A surface of the floating gate electrode adjacent the active region defines a plane, and the isolation layer is confined between the plane and the substrate. A control gate electrode is formed on a surface of the floating gate electrode opposite the active region. The control gate electrode may be formed to extend along sidewalls of the floating gate electrode towards the substrate beyond the plane defined by the surface of the floating gate electrode adjacent the active region. Related devices are also discussed.
摘要翻译：半导体存储器件通过形成从半导体衬底突出的有源区域形成，在邻近有源区域的相对侧壁的衬底上形成隔离层，以及在其相对侧壁之间的有源区域的表面上形成浮栅电极。浮栅电极被形成为延伸超过有源区表面的边缘到隔离层上。邻近有源区的浮栅电极的表面限定了一个平面，隔离层被限制在平面和衬底之间。控制栅电极形成在浮动栅电极的与有源区相对的表面上。控制栅电极可以被形成为沿着浮置栅电极的侧壁朝着衬底延伸超过由邻近有源区的浮栅的表面限定的平面。还讨论了相关设备。

17. 发明授权

US06936885B2 NAND-type flash memory devices and methods of fabricating the same 有权
公开(公告)号：US06936885B2
公开(公告)日：2005-08-30
申请号：US10921656
申请日：2004-08-19
申请人： Kwang-Shik Shin , Kyu-Charn Park , Heung-Kwun Oh , Sung-Hoi Hur , Sang-Bin Song , Jung-Dal Choi
发明人： Kwang-Shik Shin , Kyu-Charn Park , Heung-Kwun Oh , Sung-Hoi Hur , Sang-Bin Song , Jung-Dal Choi
IPC分类号： H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/76802 , H01L27/115 , H01L27/11524
摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

18. 发明授权

US06818510B2 Non-volatile memory device and method for fabricating the same 有权
公开(公告)号：US06818510B2
公开(公告)日：2004-11-16
申请号：US10704285
申请日：2003-11-06
申请人： Chang-Hyun Lee , Jung-Dal Choi , Byung-Kwan You , Sung-Hoi Hur
发明人： Chang-Hyun Lee , Jung-Dal Choi , Byung-Kwan You , Sung-Hoi Hur
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A non-volatile memory device and fabrication method thereof are provided. A floating region is formed on an active region on a substrate. Trenches define the active region. The floating region is made of an ONO layer. A gate electrode is formed on the floating region. A mask is formed on the gate electrode. A thermal oxidation is performed to make a sidewall oxide and a trench oxide on the sidewall of the gate electrode and the trench, respectively. As a result, the widths of the gate electrode and the active region become less than the width of the floating region, thereby forming protrusions at ends of the floating region. Isolation regions are formed in the trenches and include the sidewall oxide and the trench oxide. The isolation regions surround the protrusions. As a result, electric field induced on the sidewall of the floating region is decreased. Moreover, the thermal oxidation cures any damage to the sidewalls of the floating region. Accordingly, leakage current can be substantially suppressed at the boundary region between the isolation region and the floating region.

19. 发明申请

US20060033166A1 Electronic devices having partially elevated source/drain structures and related methods 审中-公开
标题翻译：具有部分升高的源极/漏极结构和相关方法的电子器件
公开(公告)号：US20060033166A1
公开(公告)日：2006-02-16
申请号：US11020311
申请日：2004-12-22
申请人： Min-Cheol Park , Sung-Hoi Hur
发明人： Min-Cheol Park , Sung-Hoi Hur
IPC分类号： H01L29/94
CPC分类号： H01L21/76877 , H01L21/28525 , H01L29/66628 , H01L29/78
摘要： Methods of forming an electronic device may include forming a gate electrode on a semiconductor substrate, and forming first and second impurity doped regions of the semiconductor substrate on opposite sides of the gate electrode. An insulating layer may be formed on the semiconductor substrate including the first and second impurity doped regions, and first and second holes may be formed in the insulating layer, with the first and second holes respectively exposing portions of the first and second impurity doped regions. In addition, first and second epitaxial semiconductor layers may be formed in the respective first and second holes on the exposed portions of the first and second impurity doped regions of the semiconductor substrate. Related devices are also discussed.
摘要翻译：形成电子器件的方法可以包括在半导体衬底上形成栅电极，以及在栅电极的相对侧上形成半导体衬底的第一和第二杂质掺杂区。可以在包括第一和第二杂质掺杂区域的半导体衬底上形成绝缘层，并且可以在绝缘层中形成第一和第二孔，其中第一和第二孔分别暴露第一和第二杂质掺杂区域的部分。此外，可以在半导体衬底的第一和第二杂质掺杂区域的暴露部分上的相应的第一和第二孔中形成第一和第二外延半导体层。还讨论了相关设备。

20. 发明授权

US07585710B2 Methods of forming electronic devices having partially elevated source/drain structures 失效
标题翻译：形成具有部分升高的源极/漏极结构的电子器件的方法
公开(公告)号：US07585710B2
公开(公告)日：2009-09-08
申请号：US11638775
申请日：2006-12-14
申请人： Min-Cheol Park , Sung-Hoi Hur
发明人： Min-Cheol Park , Sung-Hoi Hur
IPC分类号： H01L29/72
CPC分类号： H01L21/76877 , H01L21/28525 , H01L29/66628 , H01L29/78
摘要： Methods of forming an electronic device may include forming a gate electrode on a semiconductor substrate, and forming first and second impurity doped regions of the semiconductor substrate on opposite sides of the gate electrode. An insulating layer may be formed on the semiconductor substrate including the first and second impurity doped regions, and first and second holes may be formed in the insulating layer, with the first and second holes respectively exposing portions of the first and second impurity doped regions. In addition, first and second epitaxial semiconductor layers may be formed in the respective first and second holes on the exposed portions of the first and second impurity doped regions of the semiconductor substrate. Related devices are also discussed.
摘要翻译：形成电子器件的方法可以包括在半导体衬底上形成栅电极，以及在栅电极的相对侧上形成半导体衬底的第一和第二杂质掺杂区。可以在包括第一和第二杂质掺杂区域的半导体衬底上形成绝缘层，并且可以在绝缘层中形成第一和第二孔，其中第一和第二孔分别暴露第一和第二杂质掺杂区域的部分。此外，可以在半导体衬底的第一和第二杂质掺杂区域的暴露部分上的相应的第一和第二孔中形成第一和第二外延半导体层。还讨论了相关设备。

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