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11. 发明申请

US20080191292A1 METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-k GATE DIELECTRIC STACKS 有权
标题翻译：具有低电荷捕获的金属栅极和用于高k栅介质堆叠的增强的电介质可靠性特性
公开(公告)号：US20080191292A1
公开(公告)日：2008-08-14
申请号：US11673901
申请日：2007-02-12
申请人： Alessandro C. Callegari , Michael P. Chudzik , Barry P. Linder , Renee T. Mo , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Sufi Zafar
发明人： Alessandro C. Callegari , Michael P. Chudzik , Barry P. Linder , Renee T. Mo , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Sufi Zafar
IPC分类号： H01L29/49 , H01L21/3205
CPC分类号： H01L21/28088 , H01L21/28518 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665
摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.
摘要翻译：提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含金属层的底部至顶部。通过利用具有小于1.1的金属与氮的组成比的金属含氮层来实现提高的可靠性。本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。本发明还提供一种制造这种栅叠层的方法，其中改变溅射工艺的工艺条件以控制溅射沉积层内的金属和氮的比例。

12. 发明申请

US20080203485A1 STRAINED METAL GATE STRUCTURE FOR CMOS DEVICES WITH IMPROVED CHANNEL MOBILITY AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有改进的通道移动性的CMOS器件的应变金属栅结构及其形成方法
公开(公告)号：US20080203485A1
公开(公告)日：2008-08-28
申请号：US11680108
申请日：2007-02-28
申请人： Michael P. Chudzik , Wei He , Renee T. Mo , Naim Moumen , Vijay Narayanan , Dae-gyu Park , Vamsi Paruchuri
发明人： Michael P. Chudzik , Wei He , Renee T. Mo , Naim Moumen , Vijay Narayanan , Dae-gyu Park , Vamsi Paruchuri
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/78 , H01L29/7845
摘要： A gate structure for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack having a first gate dielectric layer formed over a substrate, and a first metal layer formed over the first gate dielectric layer. A second gate stack includes a second gate dielectric layer formed over the substrate and a second metal layer formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.
摘要翻译：用于互补金属氧化物半导体（CMOS）器件的栅极结构包括具有形成在衬底上的第一栅极介电层的第一栅极堆叠和形成在第一栅极介电层上的第一金属层。第二栅极堆叠包括形成在衬底上的第二栅极电介质层和形成在第二栅极介电层上的第二金属层。第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。

13. 发明申请

US20100187610A1 SEMICONDUCTOR DEVICE HAVING DUAL METAL GATES AND METHOD OF MANUFACTURE 有权
标题翻译：具有双金属门的半导体器件及其制造方法
公开(公告)号：US20100187610A1
公开(公告)日：2010-07-29
申请号：US12359520
申请日：2009-01-26
申请人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
发明人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/4966 , H01L29/517
摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.
摘要翻译：半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且第三金属层，第三金属层设置在第二中间层上。或者，省略第一金属层。制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。

14. 发明授权

US07838908B2 Semiconductor device having dual metal gates and method of manufacture 有权
标题翻译：具有双金属栅极的半导体器件及其制造方法
公开(公告)号：US07838908B2
公开(公告)日：2010-11-23
申请号：US12359520
申请日：2009-01-26
申请人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
发明人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
IPC分类号： H01L27/10
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/4966 , H01L29/517
摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.
摘要翻译：半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且第三金属层，第三金属层设置在第二中间层上。或者，省略第一金属层。制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。

15. 发明申请

US20100244206A1 METHOD AND STRUCTURE FOR THRESHOLD VOLTAGE CONTROL AND DRIVE CURRENT IMPROVEMENT FOR HIGH-K METAL GATE TRANSISTORS 审中-公开
标题翻译：用于高K金属栅极晶体管的阈值电压控制和驱动电流改进的方法和结构
公开(公告)号：US20100244206A1
公开(公告)日：2010-09-30
申请号：US12414794
申请日：2009-03-31
申请人： Huiming Bu , Michael P. Chudzik , Wei He , Rashmi Jha , Young-Hee Kim , Siddarth A. Krishnan , Renee T. Mo , Naim Moumen , Wesley C. Natzle
发明人： Huiming Bu , Michael P. Chudzik , Wei He , Rashmi Jha , Young-Hee Kim , Siddarth A. Krishnan , Renee T. Mo , Naim Moumen , Wesley C. Natzle
IPC分类号： H01L23/00 , H01L21/314
CPC分类号： H01L21/28202 , H01L21/28176 , H01L21/28185 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.
摘要翻译：形成器件的方法包括提供衬底，在衬底上形成界面层，在界面层上沉积高k电介质层，在高k电介质层上沉积氧气清除层并执行退火。高k金属栅极晶体管包括衬底，衬底上的界面层，界面层上的高k电介质层和高k电介质层上的氧清除层。

16. 发明申请

US20090294920A1 METHOD FOR FORMING DUAL HIGH-K METAL GATE USING PHOTORESIST MASK AND STRUCTURES THEREOF 有权
标题翻译：使用光电隔离膜形成双高金属栅的方法及其结构
公开(公告)号：US20090294920A1
公开(公告)日：2009-12-03
申请号：US12132146
申请日：2008-06-03
申请人： Michael P. Chudzik , Rashmi Jha , Naim Moumen , Keith Kwong Hon Wong , Ying H. Tsang
发明人： Michael P. Chudzik , Rashmi Jha , Naim Moumen , Keith Kwong Hon Wong , Ying H. Tsang
IPC分类号： H01L23/58 , H01L21/311
CPC分类号： H01L21/31133 , H01L21/31127 , H01L21/31138
摘要： Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N2/H2) or ammonia (NH3) may be used to remove the photoresist mask. With the use of the plasma nitrogen-hydrogen forming gas (N2/H2) or a plasma ammonia (NH3), no apparent organic residual is observed.
摘要翻译：公开了使用光致抗蚀剂掩模及其结构形成前端（FEOL）双高k栅极的方法。所公开方法的一个实施例包括在FEOL CMOS结构的衬底上沉积高k电介质膜，然后在其上沉积光致抗蚀剂; 根据光致抗蚀剂图案化高k电介质; 之后除去光致抗蚀剂。去除光致抗蚀剂包括使用有机溶剂，然后除去包括有机和/或碳膜的残留光致抗蚀剂。去除残留的光致抗蚀剂可以包括脱气工艺，或称为烘烤工艺。或者，可以使用形成氮气的气体（即，氮气和氢气的混合物）（N 2 / H 2）或氨（NH 3）以除去光致抗蚀剂掩模。通过使用等离子体形成氮气的气体（N 2 / H 2）或等离子体氨（NH 3），没有观察到明显的有机残留。

17. 发明授权

US07915115B2 Method for forming dual high-k metal gate using photoresist mask and structures thereof 有权
标题翻译：使用光致抗蚀剂掩模及其结构形成双高k金属栅的方法
公开(公告)号：US07915115B2
公开(公告)日：2011-03-29
申请号：US12132146
申请日：2008-06-03
申请人： Michael P. Chudzik , Rashmi Jha , Naim Moumen , Keith Kwong Hon Wong , Ying H. Tsang
发明人： Michael P. Chudzik , Rashmi Jha , Naim Moumen , Keith Kwong Hon Wong , Ying H. Tsang
IPC分类号： H01L29/72
CPC分类号： H01L21/31133 , H01L21/31127 , H01L21/31138
摘要： Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N2/H2) or ammonia (NH3) may be used to remove the photoresist mask. With the use of the plasma nitrogen-hydrogen forming gas (N2/H2) or a plasma ammonia (NH3), no apparent organic residual is observed.
摘要翻译：公开了使用光致抗蚀剂掩模及其结构形成前端（FEOL）双高k栅极的方法。所公开方法的一个实施例包括在FEOL CMOS结构的衬底上沉积高k电介质膜，然后在其上沉积光致抗蚀剂; 根据光致抗蚀剂图案化高k电介质; 之后除去光致抗蚀剂。去除光致抗蚀剂包括使用有机溶剂，然后除去包括有机和/或碳膜的残留光致抗蚀剂。去除残留的光致抗蚀剂可以包括脱气工艺，或称为烘烤工艺。或者，可以使用形成氮气的气体（即，氮气和氢气的混合物）（N 2 / H 2）或氨（NH 3）以除去光致抗蚀剂掩模。通过使用等离子体形成氮气的气体（N 2 / H 2）或等离子体氨（NH 3），没有观察到明显的有机残留。

18. 发明申请

US20090152637A1 PFET WITH TAILORED DIELECTRIC AND RELATED METHODS AND INTEGRATED CIRCUIT 有权
标题翻译：具有定制电介质的PFET及相关方法和集成电路
公开(公告)号：US20090152637A1
公开(公告)日：2009-06-18
申请号：US11955491
申请日：2007-12-13
申请人： Rick Carter , Michael P. Chudzik , Rashmi Jha , Naim Moumen
发明人： Rick Carter , Michael P. Chudzik , Rashmi Jha , Naim Moumen
IPC分类号： H01L27/00 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823842 , H01L21/82385
摘要： A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In one embodiment, the PFET includes an n-type doped silicon well (N-well), a gate stack including: a doped band engineered PFET threshold voltage (Vt) work function tuning layer over the N-well; a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer constituted by a high dielectric constant layer over the doped band engineered PFET Vt work function tuning layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; and a metal over the NFET Vt work function tuning layer.
摘要翻译：公开了一种具有由其栅极堆叠中的NFET阈值电压（Vt）功函数调谐层，相关方法和集成电路部分构成的定制电介质的PFET。在一个实施例中，PFET包括n型掺杂硅阱（N阱），栅堆叠，其包括：在N阱上的掺杂带工程化PFET阈值电压（Vt）功函数调谐层; 在掺杂带工程化的PFET Vt功函数调谐层之上的定制电介质层，由掺杂带工程化的PFET Vt功函数调谐层和n型场效应晶体管（NFET）阈值上的高介电常数层构成的调整后的介电层电压（Vt）工作功能调谐层在高介电常数层上; 和NFET Vt功能调谐层上的金属。

19. 发明授权

US08518766B2 Method of forming switching device having a molybdenum oxynitride metal gate 有权
标题翻译：形成具有氮氧化钼金属栅极的开关器件的方法
公开(公告)号：US08518766B2
公开(公告)日：2013-08-27
申请号：US13536366
申请日：2012-06-28
申请人： Nestor A. Bojarczuk , Michael P. Chudzik , Matthew W. Copel , Supratik Guha , Richard A. Haight , Vijay Narayanan , Martin P. O'Boyle , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk , Michael P. Chudzik , Matthew W. Copel , Supratik Guha , Richard A. Haight , Vijay Narayanan , Martin P. O'Boyle , Vamsi K. Paruchuri
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/3205 , H01L21/4763 , H01L21/70
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/51
摘要： A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate.
摘要翻译：场效应晶体管（FET）包括至少部分地设置在身体区域中的体区和源区。 FET还包括至少部分地设置在体区中的漏极区域和氮氧化钼（MoNO）栅极。 FET还包括具有高介电常数（k）的电介质，其布置在体区和MoNO门之间。

20. 发明授权

US07569466B2 Dual metal gate self-aligned integration 有权
标题翻译：双金属栅极自对准集成
公开(公告)号：US07569466B2
公开(公告)日：2009-08-04
申请号：US11303715
申请日：2005-12-16
申请人： Alessandro C. Callegari , Michael P. Chudzik , Bruce B. Doris , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
发明人： Alessandro C. Callegari , Michael P. Chudzik , Bruce B. Doris , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823842
摘要： A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.
摘要翻译：包括至少一个n型场效应晶体管（nFET）和至少一个p型场效应晶体管（pFET）的半导体结构，其分别包括具有nFET行为的金属栅极和pFET行为，而不包括上多晶硅栅极提供电极。本发明还提供一种制造这种半导体结构的方法。

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