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1. 发明申请

US20100244206A1 METHOD AND STRUCTURE FOR THRESHOLD VOLTAGE CONTROL AND DRIVE CURRENT IMPROVEMENT FOR HIGH-K METAL GATE TRANSISTORS 审中-公开
标题翻译：用于高K金属栅极晶体管的阈值电压控制和驱动电流改进的方法和结构
公开(公告)号：US20100244206A1
公开(公告)日：2010-09-30
申请号：US12414794
申请日：2009-03-31
申请人： Huiming Bu , Michael P. Chudzik , Wei He , Rashmi Jha , Young-Hee Kim , Siddarth A. Krishnan , Renee T. Mo , Naim Moumen , Wesley C. Natzle
发明人： Huiming Bu , Michael P. Chudzik , Wei He , Rashmi Jha , Young-Hee Kim , Siddarth A. Krishnan , Renee T. Mo , Naim Moumen , Wesley C. Natzle
IPC分类号： H01L23/00 , H01L21/314
CPC分类号： H01L21/28202 , H01L21/28176 , H01L21/28185 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.
摘要翻译：形成器件的方法包括提供衬底，在衬底上形成界面层，在界面层上沉积高k电介质层，在高k电介质层上沉积氧气清除层并执行退火。高k金属栅极晶体管包括衬底，衬底上的界面层，界面层上的高k电介质层和高k电介质层上的氧清除层。

2. 发明授权

US08035173B2 CMOS transistors with differential oxygen content high-K dielectrics 有权
标题翻译：具有差异氧含量高K电介质的CMOS晶体管
公开(公告)号：US08035173B2
公开(公告)日：2011-10-11
申请号：US12712371
申请日：2010-02-25
申请人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
发明人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L29/78
CPC分类号： H01L21/823864 , H01L21/823814 , H01L21/823857 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/4908 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.
摘要翻译：在半导体衬底上形成包含第一高k电介质部分的NFET和包含第二高k栅极电介质部分的PFET。栅极侧壁氮化物形成在NFET的栅极上，而PFET的侧壁保持没有栅极侧壁氮化物。直接在PFET栅极堆叠的侧壁上和NFET上的栅极侧壁氮化物上形成氧化物间隔物。在高温处理之后，第一和第二介质部分含有非化学计量的缺氧高k电介质材料。半导体结构在氧气环境中进行退火，在该环境中，氧气通过氧化物间隔物扩散到第二高k电介质部分。 PFET包括更高化学计量的高k电介质材料，并且NFET包含较少化学计量的高k电介质材料。本发明优化了PFET和NFET的阈值电压。

3. 发明授权

US07696036B2 CMOS transistors with differential oxygen content high-k dielectrics 失效
标题翻译：具有差异氧含量高k电介质的CMOS晶体管
公开(公告)号：US07696036B2
公开(公告)日：2010-04-13
申请号：US11763047
申请日：2007-06-14
申请人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
发明人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/823814 , H01L21/823857 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/4908 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.
摘要翻译：在半导体衬底上形成包含第一高k电介质部分的NFET和包含第二高k栅极电介质部分的PFET。栅极侧壁氮化物形成在NFET的栅极上，而PFET的侧壁保持没有栅极侧壁氮化物。直接在PFET栅极堆叠的侧壁上和NFET上的栅极侧壁氮化物上形成氧化物间隔物。在高温处理之后，第一和第二介质部分含有非化学计量的缺氧高k电介质材料。半导体结构在氧气环境中进行退火，在该环境中，氧气通过氧化物间隔物扩散到第二高k电介质部分。 PFET包括更高化学计量的高k电介质材料，并且NFET包含较少化学计量的高k电介质材料。本发明优化了PFET和NFET的阈值电压。

4. 发明申请

US20090142891A1 MASKLESS STRESS MEMORIZATION TECHNIQUE FOR CMOS DEVICES 审中-公开
标题翻译： CMOS器件的无缝应力记忆技术
公开(公告)号：US20090142891A1
公开(公告)日：2009-06-04
申请号：US11948849
申请日：2007-11-30
申请人： Young-Hee Kim , Jeffrey W. Sleight , Huiming Bu , Rick Carter , Mike Hargrove
发明人： Young-Hee Kim , Jeffrey W. Sleight , Huiming Bu , Rick Carter , Mike Hargrove
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/84 , H01L29/7843
摘要： In one embodiment, the present invention provides a method of manufacturing a semiconducting device that includes providing a silicon containing substrate having PFET device and NFET device, wherein the NFET device includes an amorphous silicon containing region; depositing a tensile strain silicon nitride layer atop the NFET device and the PFET device, wherein the silicon nitride tensile strain layer induces a tensile strain in a channel of the NFET device region; annealing to crystallize the amorphous silicon containing region, wherein the tensile strain silicon nitride layer positioned atop the PFET device confines oxygen within a channel positioned within the silicon containing substrate underlying the PFET device, wherein the oxygen within the channel shifts a threshold voltage of the PFET device towards a valence band of silicon of the silicon containing substrate; and removing the tensile strain silicon nitride layer.
摘要翻译：在一个实施例中，本发明提供一种制造半导体器件的方法，其包括提供具有PFET器件和NFET器件的含硅衬底，其中所述NFET器件包括非晶硅含硅区域; 在NFET器件和PFET器件的顶部沉积拉伸应变氮化硅层，其中氮化硅拉伸应变层在NFET器件区域的沟道中引起拉伸应变; 退火以使非晶硅含有区域结晶，其中位于PFET器件顶部的拉伸应变氮化硅层将氧气限制在位于PFET器件下面的含硅衬底内的通道内，其中通道内的氧漂移PFET的阈值电压朝向含硅衬底的硅的价带的器件; 并去除拉伸应变氮化硅层。

5. 发明申请

US20080308872A1 CMOS TRANSISTORS WITH DIFFERENTIAL OXYGEN CONTENT HIGH-K DIELECTRICS 失效
标题翻译：具有差分氧含量高K电介质的CMOS晶体管
公开(公告)号：US20080308872A1
公开(公告)日：2008-12-18
申请号：US11763047
申请日：2007-06-14
申请人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
发明人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823864 , H01L21/823814 , H01L21/823857 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/4908 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.
摘要翻译：在半导体衬底上形成包含第一高k电介质部分的NFET和包含第二高k栅极电介质部分的PFET。栅极侧壁氮化物形成在NFET的栅极上，而PFET的侧壁保持没有栅极侧壁氮化物。直接在PFET栅极堆叠的侧壁上和NFET上的栅极侧壁氮化物上形成氧化物间隔物。在高温处理之后，第一和第二介质部分含有非化学计量的缺氧高k电介质材料。半导体结构在氧气环境中进行退火，在该环境中，氧气通过氧化物间隔物扩散到第二高k电介质部分。 PFET包括更高化学计量的高k电介质材料，并且NFET包含较少化学计量的高k电介质材料。本发明优化了PFET和NFET的阈值电压。

6. 发明申请

US20100148273A1 CMOS TRANSISTORS WITH DIFFERENTIAL OXYGEN CONTENT HIGH-K DIELECTRICS 有权
标题翻译：具有差分氧含量高K电介质的CMOS晶体管
公开(公告)号：US20100148273A1
公开(公告)日：2010-06-17
申请号：US12712371
申请日：2010-02-25
申请人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
发明人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L27/092
CPC分类号： H01L21/823864 , H01L21/823814 , H01L21/823857 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/4908 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.
摘要翻译：在半导体衬底上形成包含第一高k电介质部分的NFET和包含第二高k栅极电介质部分的PFET。栅极侧壁氮化物形成在NFET的栅极上，而PFET的侧壁保持没有栅极侧壁氮化物。直接在PFET栅极堆叠的侧壁上和NFET上的栅极侧壁氮化物上形成氧化物间隔物。在高温处理之后，第一和第二介质部分含有非化学计量的缺氧高k电介质材料。半导体结构在氧气环境中进行退火，在该环境中，氧气通过氧化物间隔物扩散到第二高k电介质部分。 PFET包括更高化学计量的高k电介质材料，并且NFET包含较少化学计量的高k电介质材料。本发明优化了PFET和NFET的阈值电压。

7. 发明授权

US08383483B2 High performance CMOS circuits, and methods for fabricating same 有权
标题翻译：高性能CMOS电路及其制造方法
公开(公告)号：US08383483B2
公开(公告)日：2013-02-26
申请号：US12541562
申请日：2009-08-14
申请人： John C. Arnold , Glenn A. Biery , Alessandro C. Callegari , Tze-Chiang Chen , Michael P. Chudzik , Bruce B. Doris , Michael A. Gribelyuk , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Joseph S. Newbury , Vamsi K. Paruchuri , Michelle L. Steen
发明人： John C. Arnold , Glenn A. Biery , Alessandro C. Callegari , Tze-Chiang Chen , Michael P. Chudzik , Bruce B. Doris , Michael A. Gribelyuk , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Joseph S. Newbury , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L21/336
CPC分类号： H01L21/823857 , H01L21/823842
摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.
摘要翻译：本发明涉及互补金属氧化物半导体（CMOS）电路，其各自包含至少第一和第二栅极堆叠。第一栅极堆叠位于半导体衬底中的第一器件区域（例如，n-FET器件区域）上，并且至少从底部至顶部包括栅极介电层，金属栅极导体和含硅的门导体。第二栅极堆叠位于半导体衬底中的第二器件区域（例如，p-FET器件区域）上，并且至少包括从栅极电介质层和含硅栅极导体的底部到顶部。可以通过本发明的各种方法以集成的方式在半导体衬底上形成第一和第二栅极叠层。

8. 发明授权

US07833849B2 Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode 有权
标题翻译：一种制造半导体结构的方法，包括一个器件区域，该器件区域具有位于薄化的多晶硅电极顶部的金属栅电极
公开(公告)号：US07833849B2
公开(公告)日：2010-11-16
申请号：US11323564
申请日：2005-12-30
申请人： Alessandro C. Callegari , Tze-Chiang Chen , Michael P. Chudzik , Bruce B. Doris , Young-Hee Kim , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen , Ying Zhang
发明人： Alessandro C. Callegari , Tze-Chiang Chen , Michael P. Chudzik , Bruce B. Doris , Young-Hee Kim , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen , Ying Zhang
IPC分类号： H01L21/62
CPC分类号： H01L21/823857 , H01L21/28044 , H01L21/28088 , H01L21/823842 , H01L29/4925 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： A method of fabricating semiconductor structure is provided in which at least one nFET device and a least one pFET device are formed on a semiconductor substrate. Each device region formed includes a dielectric stack that has a net dielectric constant equal to or greater than silicon dioxide. Gate stacks are provided on each of the dielectric stacks, wherein one of the gate stacks includes a metal gate electrode located atop a surface of a thinned polygate electrode.
摘要翻译：提供一种制造半导体结构的方法，其中至少一个nFET器件和至少一个pFET器件形成在半导体衬底上。形成的每个器件区域包括具有等于或大于二氧化硅的净介电常数的电介质叠层。在每个电介质堆叠上设置栅极堆叠，其中栅极堆叠中的一个包括位于变薄的多晶硅电极的表面顶部的金属栅电极。

9. 发明申请

US20100041221A1 HIGH PERFORMANCE CMOS CIRCUITS, AND METHODS FOR FABRICATING SAME 有权
标题翻译：高性能CMOS电路及其制造方法
公开(公告)号：US20100041221A1
公开(公告)日：2010-02-18
申请号：US12541562
申请日：2009-08-14
申请人： John C. Arnold , Glenn A. Biery , Alessandro C. Callegari , Tze-Chiang Chen , Michael P. Chudzik , Bruce B. Doris , Michael A. Gribelyuk , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Joseph S. Newbury , Vamsi K. Paruchuri , Michelle L. Steen
发明人： John C. Arnold , Glenn A. Biery , Alessandro C. Callegari , Tze-Chiang Chen , Michael P. Chudzik , Bruce B. Doris , Michael A. Gribelyuk , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Joseph S. Newbury , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L21/28
CPC分类号： H01L21/823857 , H01L21/823842
摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.
摘要翻译：本发明涉及互补金属氧化物半导体（CMOS）电路，其各自包含至少第一和第二栅极堆叠。第一栅极堆叠位于半导体衬底中的第一器件区域（例如，n-FET器件区域）上，并且至少从底部至顶部包括栅极介电层，金属栅极导体和含硅的门导体。第二栅极堆叠位于半导体衬底中的第二器件区域（例如，p-FET器件区域）上，并且至少包括从栅极电介质层和含硅栅极导体的底部到顶部。可以通过本发明的各种方法以集成的方式在半导体衬底上形成第一和第二栅极叠层。

10. 发明授权

US09287136B2 FinFET field-effect transistors with atomic layer doping 有权
标题翻译：具有原子层掺杂的FinFET场效应晶体管
公开(公告)号：US09287136B2
公开(公告)日：2016-03-15
申请号：US13606873
申请日：2012-09-07
申请人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
发明人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
IPC分类号： H01L29/78 , H01L27/088 , H01L21/20 , H01L21/24 , H01L21/314 , H01L21/02 , H01L29/36 , H01L21/225 , H01L29/66 , H01L29/165
CPC分类号： H01L21/31 , H01L21/0228 , H01L21/2254 , H01L29/165 , H01L29/365 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66803 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.
摘要翻译：公开了使用原子层掺杂工艺制造的场效应晶体管。根据原子层掺杂方法的实施方案，制备半导体表面和掺杂剂气体混合物。此外，通过在小于500托的压力和300℃至750℃的温度下将掺杂剂气体混合物施加到半导体表面，在半导体表面上生长掺杂剂层。掺杂剂层包括在与半导体表面上的原子反应的每立方厘米的最小4×10 20有源掺杂剂原子使得反应的原子增加了半导体表面的导电性。

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