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11. 发明申请

US20080010433A1 METHOD AND APPARATUS FOR EFFICIENTLY ACCESSING BOTH ALIGNED AND UNALIGNED DATA FROM A MEMORY 有权
标题翻译：从存储器中有效地访问两个对齐和对数据的方法和装置
公开(公告)号：US20080010433A1
公开(公告)日：2008-01-10
申请号：US11837241
申请日：2007-08-10
申请人： Eric Fluhr , Sheldon Levenstein
发明人： Eric Fluhr , Sheldon Levenstein
IPC分类号： G06F9/34
CPC分类号： G06F12/04 , G06F12/0846 , G06F12/0886
摘要： A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the cache's internal organization, the address range required by the requested data can be covered by one odd and one even segment of the cache, where the odd segment is always at the base address created by the summation of the source operands and set to the odd segment, and the even address is created by summation of the source operands plus an offset value equivalent to the size of the cache line. This structural regularity is used to efficiently generate both the even and odd addresses in parallel to retrieve the desired data.
摘要翻译：一种用于在访问内存时改进访问时间的技术，例如从缓存访问数据时。通过与高速缓存的内部组织结合使用指定的存储器地址的独特操作和使用，所请求的数据所需的地址范围可以由高速缓存的一个奇数和一个偶数段覆盖，其中奇数段总是在基地地址由源操作数的总和创建并设置为奇数段，偶数地址是通过源操作数的加法加上与缓存行大小相等的偏移值来创建的。这种结构规律性用于有效地同时产生偶数和奇数地址以检索所需数据。

12. 发明申请

US20060184741A1 Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor 有权
标题翻译：用于在SMT处理器的线程之间共享缓存中的数据的方法，装置和计算机程序产品
公开(公告)号：US20060184741A1
公开(公告)日：2006-08-17
申请号：US11055820
申请日：2005-02-11
申请人： David Hrusecky , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
发明人： David Hrusecky , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F12/084 , G06F12/0862
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for sharing data in a cache among multiple threads in a simultaneous multi-threaded (SMT) processor. The SMT processor executes multiple threads concurrently during each clock cycle. The cache is dynamically allocated for use among the multiple threads. Portions of the cache are capable of being designated to store private data that is used exclusively by only a first one of the threads. The portions of the cache are capable of being designated to store shared data that can be used by any one of the multiple threads. The size of the portions can be changed dynamically during execution of the threads.
摘要翻译：在用于在同时多线程（SMT）处理器中的多个线程之间的高速缓存中共享数据的数据处理系统中公开了一种方法，装置和计算机程序产品。 SMT处理器在每个时钟周期内同时执行多个线程。动态分配缓存以在多个线程之间使用。高速缓存的一部分能够被指定为仅存储第一个线程专用的专用数据。高速缓存的部分能够被指定为存储可由多个线程中的任何一个使用的共享数据。在执行线程期间，可以动态地更改部分的大小。

13. 发明申请

US20060184739A1 Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch 有权
公开(公告)号：US20060184739A1
公开(公告)日：2006-08-17
申请号：US11055818
申请日：2005-02-11
申请人： Scott Frommer , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
发明人： Scott Frommer , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F12/0897
摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.

14. 发明申请

US20060179227A1 Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class 有权
标题翻译：允许N路组关联高速缓存的机制和装置，实现混合伪LRU替换算法，以使N L1未命中提取请求同时运行，而不管其一致等级
公开(公告)号：US20060179227A1
公开(公告)日：2006-08-10
申请号：US11054293
申请日：2005-02-09
申请人： David Hrusecky , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
发明人： David Hrusecky , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F12/124 , G06F12/125 , G06F12/127
摘要： A method, system, and computer program product for supporting multiple fetch requests to the same congruence class in an n-way set associative cache. Responsive to receiving an incoming fetch instruction at a load/store unit, outstanding valid fetch entries in the n-way set associative cache that have the same cache congruence class as the incoming fetch instruction are identified. SetIDs in used by these identified outstanding valid fetch entries are determined. A resulting setID is assigned to the incoming fetch instruction based on the identified setIDs, wherein the resulting setID assigned is a setID not currently in use by the outstanding valid fetch entries. The resulting setID for the incoming fetch instruction is written in a corresponding entry in the n-way set associative cache.
摘要翻译：一种方法，系统和计算机程序产品，用于在n路组关联高速缓存中支持对同一个同余类的多个提取请求。响应于在加载/存储单元处接收到传入的取指令，识别n路组关联高速缓冲存储器中具有与传入获取指令相同的高速缓存一致类的未完成的有效提取条目。确定这些识别的未完成的有效提取条目使用的SetID。所得到的setID被分配给基于所识别的setID的传入获取指令，其中分配的所得到的setID是未被提交的有效提取条目当前未使用的setID。用于传入提取指令的结果setID写入n路组关联高速缓存中的相应条目。

15. 发明申请

US20060179221A1 System and method for tracking changes in L1 data cache directory 有权
标题翻译：用于跟踪L1数据缓存目录中的更改的系统和方法
公开(公告)号：US20060179221A1
公开(公告)日：2006-08-10
申请号：US11054273
申请日：2005-02-09
申请人： Sheldon Levenstein , Anthony Saporito
发明人： Sheldon Levenstein , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0855
摘要： Method, system and computer program product for tracking changes in an L1 data cache directory. A method for tracking changes in an L1 data cache directory determines if data to be written to the L1 data cache is to be written to an address to be changed from an old address to a new address. If it is determined that the data to be written is to be written to an address to be changed, a determination is made if the data to be written is associated with the old address or the new address. If it is determined that the data is to be written to the new address, the data is allowed to be written to the new address following a prescribed delay after the address to be changed is changed. The method is preferably implemented in a system that provides a Store Queue (STQU) design that includes a Content Addressable Memory (CAM)-based store address tracking mechanism that includes early and late write CAM ports. The method eliminates time windows and the need for an extra copy of the L1 data cache directory.
摘要翻译：方法，系统和计算机程序产品，用于跟踪L1数据缓存目录中的更改。用于跟踪L1数据高速缓存目录中的变化的方法确定要写入L1数据高速缓存的数据是否被写入要从旧地址改变到新地址的地址。如果确定要写入的数据要写入要改变的地址，则确定要写入的数据是否与旧地址或新地址相关联。如果确定要将数据写入新地址，则在要更改的地址改变之后，允许将数据写入到遵循规定延迟的新地址。该方法优选地在提供包括基于内容寻址存储器（CAM）的存储地址跟踪机制的存储队列（STQU）设计的系统中实现，该机制包括早期和晚期写入CAM端口。该方法消除了时间窗口，并需要额外的L1数据高速缓存目录副本。

16. 发明申请

US20060085603A1 Processor, data processing system and method for synchronzing access to data in shared memory 有权
标题翻译：处理器，数据处理系统和方法，用于同步共享存储器中数据的访问
公开(公告)号：US20060085603A1
公开(公告)日：2006-04-20
申请号：US10965113
申请日：2004-10-14
申请人： Guy Guthrie , Sheldon Levenstein , William Starke , Derek Williams
发明人： Guy Guthrie , Sheldon Levenstein , William Starke , Derek Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3851 , G06F12/0811 , G06F12/0831 , G06F12/0855
摘要： A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional instruction, buffers a corresponding store operation, sequencer logic associated with the store queue. The sequencer logic, responsive to receipt of a latency indication indicating that resolution of the store-conditional operation as passing or failing is subject to significant latency, invalidates, prior to resolution of the store-conditional operation, a cache line in the store-through upper level cache to which a load-reserve operation previously bound.
摘要翻译：一种用于多处理器数据处理系统的处理单元，包括存储器上级缓存器，取指令执行指令排序单元，执行存储条件指令以确定存储目标地址的至少一个指令执行单元，存储器在存储条件指令的执行之后，缓存与存储队列相关联的对应存储操作，定序器逻辑的队列。定序器逻辑响应于指示存储条件操作的解析作为传递或失败的等待时间指示受到重大等待时间的影响，在存储条件操作的解析之前无效，存储器中的高速缓存行加载预备操作先前绑定到的高级缓存。

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