专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20090212366A1 CONTACT SCHEME FOR FINFET STRUCTURES WITH MULTIPLE FINs 有权
标题翻译： FINFET结构的接触方案
公开(公告)号：US20090212366A1
公开(公告)日：2009-08-27
申请号：US12434233
申请日：2009-05-01
申请人： Leland Chang , Wilfried E. Haensch , Meikei Ieong , Ghavam Shahidi , Huiling Shang
发明人： Leland Chang , Wilfried E. Haensch , Meikei Ieong , Ghavam Shahidi , Huiling Shang
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795
摘要： A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. In accordance with the present invention, the inventive structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together.
摘要翻译：提供了一种具有融合在一起而没有源极/漏极接触焊盘或局部互连的多个FIN的具有FINFET的结构。根据本发明，本发明的结构包括在衬底的表面上方延伸的多个半导电体（即，FIN）。常见的图案化栅极堆叠围绕多个半导体本体，并且含氮化物的间隔物位于公共图案化栅叠层的侧壁上。使用外延半导体层将每个半导电体合并在一起。

12. 发明授权

US08080838B2 Contact scheme for FINFET structures with multiple FINs 有权
标题翻译：具有多个FIN的FINFET结构的接触方案
公开(公告)号：US08080838B2
公开(公告)日：2011-12-20
申请号：US12434233
申请日：2009-05-01
申请人： Leland Chang , Wilfried E. Haensch , Meikei Ieong , Ghavam Shahidi , Huiling Shang
发明人： Leland Chang , Wilfried E. Haensch , Meikei Ieong , Ghavam Shahidi , Huiling Shang
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795
摘要： A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. The structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together.
摘要翻译：提供了一种具有融合在一起而没有源极/漏极接触焊盘或局部互连的多个FIN的具有FINFET的结构。该结构包括在衬底的表面上方延伸的多个半导电体（即，FIN）。常见的图案化栅极堆叠围绕多个半导体本体，并且含氮化物的间隔物位于公共图案化栅叠层的侧壁上。使用外延半导体层将每个半导电体合并在一起。

13. 发明申请

US20070287256A1 Contact scheme for FINFET structures with multiple FINs 审中-公开
标题翻译：具有多个FIN的FINFET结构的接触方案
公开(公告)号：US20070287256A1
公开(公告)日：2007-12-13
申请号：US11448702
申请日：2006-06-07
申请人： Leland Chang , Wilfried E. Haensch , Meikei Ieong , Ghavam Shahidi , Huiling Shang
发明人： Leland Chang , Wilfried E. Haensch , Meikei Ieong , Ghavam Shahidi , Huiling Shang
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795
摘要： A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. In accordance with the present invention, the inventive structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together.
摘要翻译：提供了一种具有融合在一起而没有源极/漏极接触焊盘或局部互连的多个FIN的具有FINFET的结构。根据本发明，本发明的结构包括在衬底的表面上方延伸的多个半导电体（即，FIN）。常见的图案化栅极堆叠围绕多个半导体本体，并且含氮化物的间隔物位于公共图案化栅叠层的侧壁上。使用外延半导体层将每个半导电体合并在一起。

14. 发明申请

US20060105507A1 Method to form Si-containing SOI and underlying substrate with different orientations 失效
标题翻译：形成含Si的SOI和具有不同取向的下层衬底的方法
公开(公告)号：US20060105507A1
公开(公告)日：2006-05-18
申请号：US10992150
申请日：2004-11-18
申请人： Meikei Ieong , Devendra Sadana , Ghavam Shahidi
发明人： Meikei Ieong , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L21/84
CPC分类号： H01L21/76251 , H01L21/2007
摘要： A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing layers or through an interface located between the two Si-containing layers.
摘要翻译：一种形成包含上层含Si层和下层含Si层的混合SOI衬底的方法，其中上层含Si层和下层含Si层具有不同的结晶取向。根据本发明，掩埋绝缘区域可以位于一个含硅层内或通过位于两个含Si层之间的界面。

15. 发明授权

US07713807B2 High-performance CMOS SOI devices on hybrid crystal-oriented substrates 失效
标题翻译：高性能CMOS SOI器件在混合晶体取向衬底上
公开(公告)号：US07713807B2
公开(公告)日：2010-05-11
申请号：US11958877
申请日：2007-12-18
申请人： Bruce B. Doris , Kathryn W. Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey W. Sleight , Min Yang
发明人： Bruce B. Doris , Kathryn W. Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey W. Sleight , Min Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/76275 , H01L21/823807 , H01L21/84
摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.
摘要翻译：提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

16. 发明申请

US20100112800A1 CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS 有权
标题翻译： CMOS结构及其使用多种晶体取向和栅极材料制造的方法
公开(公告)号：US20100112800A1
公开(公告)日：2010-05-06
申请号：US12683535
申请日：2010-01-07
申请人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
发明人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/28
CPC分类号： H01L21/28079 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/6659
摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.
摘要翻译：制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。平坦化层位于第二栅极材料层上。平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。也可以在第一栅极叠层上形成蚀刻停止层。所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

17. 发明授权

US07619300B2 Super hybrid SOI CMOS devices 失效
标题翻译：超级混合SOI CMOS器件
公开(公告)号：US07619300B2
公开(公告)日：2009-11-17
申请号：US12434247
申请日：2009-05-01
申请人： Meikei Ieong , Qiqing C. Ouyang
发明人： Meikei Ieong , Qiqing C. Ouyang
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207 , H01L29/7843
摘要： The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer. The dielectric material within the trench isolation region has lower stress compared to that is used in conventional STI process and it is laterally abuts at least the second stressed semiconductor surface layer and extends to an upper surface of the trench isolation region.
摘要翻译：本发明提供由混合取向的应力通道构成的半导体结构。特别地，半导体结构包括第一有源区，其具有位于掩埋绝缘材料的表面上的第一晶体取向的第一应力半导体表面层和具有位于第二晶体取向的第二应力半导体表面层的第二有源区在电介质材料的表面上。沟槽隔离区域位于第一和第二有源区域之间，并且沟槽隔离区域部分地填充有沟槽电介质材料和位于所述第二应力半导体表面层下方的电介质材料。与常规STI工艺中使用的沟槽隔离区域中的电介质材料相比具有较低的应力，并且它至少侧向邻接第二应力半导体表面层并且延伸到沟槽隔离区域的上表面。

18. 发明授权

US07605447B2 Highly manufacturable SRAM cells in substrates with hybrid crystal orientation 有权
标题翻译：具有混合晶体取向的基板中的高度可制造的SRAM单元
公开(公告)号：US07605447B2
公开(公告)日：2009-10-20
申请号：US11162780
申请日：2005-09-22
申请人： Bruce B. Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
发明人： Bruce B. Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
IPC分类号： H01L29/06 , H01L29/04 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903 , Y10S438/973
摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.
摘要翻译：本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于传输栅晶体管。

19. 发明授权

US07528056B2 Low-cost strained SOI substrate for high-performance CMOS technology 有权
标题翻译：低成本应变SOI衬底，用于高性能CMOS技术
公开(公告)号：US07528056B2
公开(公告)日：2009-05-05
申请号：US11622543
申请日：2007-01-12
申请人： Meikei Ieong , Douglas C. La Tulipe, Jr. , Leathen Shi , Anna W. Topol , James Vichiconti , Albert M. Young
发明人： Meikei Ieong , Douglas C. La Tulipe, Jr. , Leathen Shi , Anna W. Topol , James Vichiconti , Albert M. Young
IPC分类号： H01L21/36 , H01L21/20
CPC分类号： H01L21/02658 , H01L21/02667 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/78 , H01L29/7843
摘要： A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the Si regions have been strained. The inventive method includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polaity (tensile or compressive) of the stress can be controlled by the type and thickness of the stress films.
摘要翻译：提供了一种制造应变绝缘体上半导体（SSOI）结构的成本有效和简单的方法，其避免了外延生长和随后的晶片接合处理步骤。根据本发明，使用应变记忆技术在SOI衬底上产生应变半导体区域。形成在应变半导体区域上的晶体管具有更高的载流子迁移率，因为Si区域已经变形。本发明的方法包括（i）离子注入以产生薄的非晶化层，（ii）在非晶化层上沉积高应力膜，（iii）热退火以使非晶化层重结晶，和（iv）去除应力电影。由于在再结晶过程中SOI衬底处于应力状态，所以最终的半导体层也将受到应力。应力的量和应力的极性（拉伸或压缩）可以通过应力膜的类型和厚度来控制。

20. 发明授权

US07494861B2 Method for metal gated ultra short MOSFET devices 失效
标题翻译：金属门极超短MOSFET器件的方法
公开(公告)号：US07494861B2
公开(公告)日：2009-02-24
申请号：US12013704
申请日：2008-01-14
申请人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
发明人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7838 , H01L21/28017 , H01L29/105
摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.
摘要翻译：适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。体层掺杂了与地平面相反的杂质。栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式