专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5963837A Method of planarizing the semiconductor structure 失效
标题翻译：平面化半导体结构的方法
公开(公告)号：US5963837A
公开(公告)日：1999-10-05
申请号：US846924
申请日：1997-04-30
申请人： Matthias Ilg , Dirk Tobben , Peter Weigand
发明人： Matthias Ilg , Dirk Tobben , Peter Weigand
IPC分类号： H01L21/3205 , H01L21/3105 , H01L21/316 , H01L21/768 , H01L29/78 , H01L21/02
CPC分类号： H01L21/76819 , H01L21/31051 , H01L21/31053
摘要： A method for planarizing a semiconductor structure having a first surface region with a high aspect ratio topography and a second surface region with a low aspect ratio topography. A flowable material is deposited over the first and second surface regions of the structure. A portion of the material fills gaps in the high aspect ratio topography to form a substantially planar surface over the high aspect ratio topography. A doped layer, for example phosphorus doped glass, is formed over the flowable oxide material. The doped layer is disposed over the high aspect ratio and over the low aspect ratio regions. Upper surface portions over the low aspect ratio region are higher than an upper surface of the flowable material. The upper portion of the doped layer is removed over both the first and second surface portions to form a layer with a substantially planar surface above both the high aspect ratio region and the low aspect ratio region. The method is used for filling gaps, such as gaps between adjacent gate electrodes formed in a gate electrode surface region of a semiconductor structure.
摘要翻译：一种用于平面化具有高纵横比拓扑的第一表面区域和具有低纵横比拓扑的第二表面区域的半导体结构的方法。可流动材料沉积在结构的第一和第二表面区域上。材料的一部分填充高纵横比拓扑中的间隙，以在高纵横比拓扑上形成基本平坦的表面。在可流动氧化物材料上形成掺杂层，例如磷掺杂玻璃。掺杂层设置在高纵横比和低纵横比区域之上。低纵横比区域上的上表面部分高于可流动材料的上表面。在第一和第二表面部分上去除掺杂层的上部，以形成在高纵横比区域和低纵横比区域之上具有基本平坦表面的层。该方法用于填充间隙，例如形成在半导体结构的栅电极表面区域中的相邻栅电极之间的间隙。

12. 发明授权

US06492688B1 Dual work function CMOS device 失效
标题翻译：双工功能CMOS器件
公开(公告)号：US06492688B1
公开(公告)日：2002-12-10
申请号：US09260937
申请日：1999-03-02
申请人： Matthias Ilg
发明人： Matthias Ilg
IPC分类号： H01L2976
CPC分类号： H01L27/0925 , H01L21/28061 , H01L21/823842
摘要： A method for forming a CMOS device. The method includes forming a gate oxide over a surface of a semiconductor substrate. A first doped layer is formed over the gate oxide. The first doped layer is lithographically patterned comprising selectively removing a portion of such first doped layer to expose a first portion of the gate oxide with the first doped layer remaining disposed over a second laterally positioned portion of the gate oxide. A second doped is deposited over the patterned first doped layer, such second doped layer having a dopant different from, for example a conductivity type opposite to, the dopant of the first doped layer. A portion of the second doped layer is deposited over the exposed first portion of the gate oxide and over the first doped layer to provide a pair of vertically positioned regions. A lower region comprises a portion of the first doped layer and an upper region comprising a portion of the second doped layer. The second doped layer is lithographically patterned to form a pair of laterally spaced gate electrodes for the transistors, one of such gates comprising the patterned first doped layer and the other one of the gates comprising the patterned pair of vertically positioned regions.
摘要翻译：一种用于形成CMOS器件的方法。该方法包括在半导体衬底的表面上形成栅极氧化物。在栅极氧化物上形成第一掺杂层。第一掺杂层被光刻图案化，包括选择性地去除这种第一掺杂层的一部分以暴露栅极氧化物的第一部分，其中第一掺杂层保留设置在栅极氧化物的第二横向定位部分上。第二掺杂沉积在图案化的第一掺杂层上，这种第二掺杂层具有不同于例如与第一掺杂层的掺杂剂相反的导电类型的掺杂剂的掺杂剂。第二掺杂层的一部分沉积在栅极氧化物的暴露的第一部分上并在第一掺杂层上方，以提供一对垂直定位的区域。下部区域包括第一掺杂层的一部分和包括第二掺杂层的一部分的上部区域。第二掺杂层被光刻图案化以形成用于晶体管的一对横向隔开的栅电极，其中一个这样的栅极包括图案化的第一掺杂层，另一个栅极包括图案化的一对垂直定位区域。

13. 发明授权

US06376348B1 Reliable polycide gate stack with reduced sheet resistance and thickness 失效
标题翻译：可靠的多晶硅栅极叠层，薄层电阻和厚度降低
公开(公告)号：US06376348B1
公开(公告)日：2002-04-23
申请号：US08940235
申请日：1997-09-30
申请人： Martin Schrems , Matthias Ilg
发明人： Martin Schrems , Matthias Ilg
IPC分类号： H01L213205
CPC分类号： H01L27/10873 , H01L21/28061 , H01L21/823443 , H01L29/4933
摘要： Formation of a gate having a polysilicon and silicide layer thereover with reduced resistance and reduced thickness is provided. The polysilicon layer is annealed to diffuse the dopants out from the surface to reduce the dopant concentration to below the level which causes metal rich interface. Thus, a metal silicide layer can be deposited without an intrinsic poly cap layer or requiring the poly to having a decreased dopant concentration. As such, a thinner gate stack having lower sheet resistance and improved reliability is achieved.
摘要翻译：提供了具有减小的电阻和减小的厚度的具有多晶硅和硅化物层的栅极的形成。退火多晶硅层以将掺杂剂从表面扩散出来，以将掺杂剂浓度降低至低于导致富金属界面的水平。因此，可以沉积金属硅化物层而不需要固有的多晶硅覆盖层，或者要求多晶硅具有降低的掺杂剂浓度。因此，实现了具有较低的薄层电阻和改进的可靠性的较薄的栅极叠层。

14. 发明授权

US06262448B1 Memory cell having trench capacitor and vertical, dual-gated transistor 失效
标题翻译：存储单元具有沟槽电容器和垂直双门控晶体管
公开(公告)号：US06262448B1
公开(公告)日：2001-07-17
申请号：US09302756
申请日：1999-04-30
申请人： Gerhard Enders , Matthias Ilg , Lothar Risch , Dietrich Widmann
发明人： Gerhard Enders , Matthias Ilg , Lothar Risch , Dietrich Widmann
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876
摘要： A DRAM cell is disposed in an electrically isolated region of a semiconductor body. The cell includes a storage capacitor disposed in a trench. The capacitor is disposed entirely within the isolated region of the semiconductor body. The cell includes a transistor disposed in the isolated region. The transistor has a pair of gates. A word line is provided for addressing the cell. The word line has an electrical contact region to the transistor. The word line contact region is disposed entirely within the isolated region of the semiconductor body. The transistor has an active area. The active area has source, drain, and channel regions. The active area is disposed entirely within the isolated region of the semiconductor body. A bit line is provided for the cell. The bit line is in electrical contact with the gates of the transistor at a pair of bit line contact regions. Both such bit line contact regions are disposed entirely within the isolated region of the cell. With such an arrangement a DRAM cell is provided having a relatively occupies a relatively small amount of surface area of the semiconductor body.
摘要翻译： DRAM单元设置在半导体本体的电隔离区域中。电池包括设置在沟槽中的存储电容器。电容器完全设置在半导体本体的隔离区域内。电池包括设置在隔离区域中的晶体管。晶体管有一对门。提供字线用于寻址单元。字线具有到晶体管的电接触区域。字线接触区域完全设置在半导体本体的隔离区域内。晶体管有一个有源区。有源区域有源极，漏极和沟道区域。有源区域完全设置在半导体本体的隔离区域内。为单元提供位线。位线在一对位线接触区域与晶体管的栅极电接触。两个这样的位线接触区域完全设置在电池的隔离区域内。通过这样的布置，提供了DRAM单元，其具有相对占据半导体本体的较小量的表面积。

15. 发明授权

US6057250A Low temperature reflow dielectric-fluorinated BPSG 失效
标题翻译：低温回流电介质氟化BPSG
公开(公告)号：US6057250A
公开(公告)日：2000-05-02
申请号：US14431
申请日：1998-01-27
申请人： Markus Kirchhoff , Ashima Chakravarti , Matthias Ilg , Kevin A. McKinley , Son V. Nguyen , Michael J. Shapiro
发明人： Markus Kirchhoff , Ashima Chakravarti , Matthias Ilg , Kevin A. McKinley , Son V. Nguyen , Michael J. Shapiro
IPC分类号： H01L21/31 , C23C16/40 , H01L21/316 , H01L21/225 , H01L21/469
CPC分类号： H01L21/02271 , C23C16/401 , H01L21/02131 , H01L21/02211 , H01L21/31625 , H01L21/31629
摘要： An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. It is a preferred method of the invention to perform the deposition at a temperature of about 750-850.degree. C. and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface. A F-BPSG glass and semiconductor wafers having a layer of fluorine doped BPSG thereon formed by the method and apparatus of the invention are also provided.
摘要翻译：提供了一种用于在半导体器件上使用低压化学气相沉积工艺形成氟掺杂硼磷硅酸（F-BPSG）玻璃的装置和方法。 F-BPSG玻璃在基板上表现出基本上无空隙和无颗粒的层，其结构具有窄至0.10微米的间隙，纵横比为6:1。反应物气体包括硼和磷掺杂剂的源，氧和TEOS和FTES的混合物。在低压CVD工艺中使用TEOS和FTES的混合物提供具有上述增强特性的F-BPSG层。本发明的优选方法是在约750-850℃的温度和1至3托的压力下进行沉积，以在沉积过程中提供F-BPSG的原位回流。在相同的化学气相沉积室中的相似条件下还优选退火以进一步平坦化F-BPSG表面。还提供了通过本发明的方法和装置形成的具有氟掺杂BPSG层的F-BPSG玻璃和半导体晶片。

16. 发明授权

US06492282B1 Integrated circuits and manufacturing methods 失效
标题翻译：集成电路和制造方法
公开(公告)号：US06492282B1
公开(公告)日：2002-12-10
申请号：US08846925
申请日：1997-04-30
申请人： Dirk Tobben , Peter Weigand , Matthias Ilg
发明人： Dirk Tobben , Peter Weigand , Matthias Ilg
IPC分类号： H01L21316
CPC分类号： H01L21/31051 , H01L21/76801 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76837
摘要： A method of filling gaps between adjacent gate electrodes of a semiconductor structure. A self-planarizing material is deposited over the structure. A first portion of such material flow between the gate electrode to fill the gaps and a second portion of such material becomes deposited over tops of the gate electrodes and over the gaps to form a layer with a substantially planar surface. A phosphorous dopant is formed in the second portion of the self-planarizing material. Thus, relatively small gaps may be filled effectively with a layer having a very planar surface for subsequent photolithography. The phosphorous dopant provides gettering to remove adverse effects of alkali contaminant ions which may enter the gap filling material. The dielectric constant of the material filing the gaps, i.e., the first portion of the gap filling material, being substantially free of such contaminants, has a relatively low dielectric constant thereby reducing electrical coupling between adjacent electrodes. The self-planarizing material is a flowable material. The flowable oxide may be spun on or may be deposited by gaseous deposition. The phosphorous dopant may be provided by, for example: implanting phosphorous ions into the second portion of the self-planarizing layer and heating the material to both cure such material and activate the phosphorous ions; depositing a phosphorous doped layer over the layer of self-planarizing material, heating the structure to out-diffuse the phosphorous dopant into the second portion of the self-planarizing material and selectively removing the deposited layer; or by curing the spun-on self-planarizing material in a phosphine environment.
摘要翻译：一种在半导体结构的相邻栅电极之间填充间隙的方法。在该结构上沉积自平面化材料。这种材料的第一部分在栅极电极之间流动以填充间隙，并且这种材料的第二部分沉积在栅电极的顶部上并在间隙上沉积以形成具有基本平坦表面的层。在自平面化材料的第二部分中形成磷掺杂剂。因此，可以用具有非常平坦的表面的层有效地填充相对小的间隙用于随后的光刻。磷掺杂剂提供吸气以除去可能进入间隙填充材料的碱性污染物离子的不利影响。填充间隙的材料的介电常数，即间隙填充材料的第一部分基本上没有这种污染物，具有相对低的介电常数，从而减少相邻电极之间的电耦合。自平面化材料是可流动的材料。可流动的氧化物可以通过气相沉积或在其上沉积。磷掺杂剂可以通过例如：将磷离子注入到自平坦化层的第二部分中并加热材料以固化这种材料并激活磷离子来提供磷掺杂剂; 在所述自平面化材料层上沉积磷掺杂层，加热所述结构以将所述磷掺杂剂扩散到所述自平面化材料的第二部分中并选择性地去除所述沉积层; 或通过在磷化氢环境中固化纺丝自平面化材料。

17. 发明授权

US5935873A Deposition of carbon into nitride layer for improved selectivity of oxide to nitride etchrate for self aligned contact etching 失效
标题翻译：将碳沉积到氮化物层中，以提高氧化物对氮化物蚀刻的选择性，用于自对准接触蚀刻
公开(公告)号：US5935873A
公开(公告)日：1999-08-10
申请号：US939148
申请日：1997-09-29
申请人： Bruno Spuler , Juergen Wittmann , Martin Gutsche , Wolfgang Bergner , Matthias Ilg
发明人： Bruno Spuler , Juergen Wittmann , Martin Gutsche , Wolfgang Bergner , Matthias Ilg
IPC分类号： H01L21/28 , H01L21/265 , H01L21/302 , H01L21/318 , H01L21/3213 , H01L21/60 , C23C14/00 , C23C14/48
CPC分类号： H01L21/76897 , H01L21/3185
摘要： A method for forming a Self Aligned Contact in a semiconductor device includes incorporating carbon into a nitride layer during or following the formation of the nitride layer on a semiconductor substrate.
摘要翻译：在半导体器件中形成自对准接触的方法包括在半导体衬底上形成氮化物层期间或之后将碳结合到氮化物层中。

18. 发明授权

US5770469A Method for forming semiconductor structure using modulation doped silicate glasses 失效
标题翻译：使用调制掺杂硅酸盐玻璃形成半导体结构的方法
公开(公告)号：US5770469A
公开(公告)日：1998-06-23
申请号：US578165
申请日：1995-12-29
申请人： Kevin J. Uram , John K. Shugrue , Nathan P. Sandler , Son Van Nguyen , Matthias Ilg
发明人： Kevin J. Uram , John K. Shugrue , Nathan P. Sandler , Son Van Nguyen , Matthias Ilg
IPC分类号： C23C16/40 , C23C16/44 , C23C16/455 , C23C16/50 , H01L21/316 , H01L21/768 , H01L23/29
CPC分类号： C23C16/45523 , C23C16/401 , C23C16/45508 , C23C16/50 , H01L21/02126 , H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31608 , H01L21/76837 , H01L23/291 , H01L2924/0002 , Y10S438/982
摘要： A method of fabricating a semiconductor structure utilizing doped silicate glass on a substrate of a wafer. The method includes the step forming a modulation doped silicate glass structure over a first layer of the wafer. The modulation doped silicate glass structure is formed by depositing at least two alternating layers of heavily-doped silicate glass and lightly-doped silicate glass over the first layer. Both the heavily-doped silicate glass and lightly-doped silicate glass layers may comprise glass doped with both a first dopant and a second dopant. The first dopant may represent, for example, phosphorous, and the second dopant may represent, for example, boron.
摘要翻译：一种在晶片的衬底上制造利用掺杂的硅酸盐玻璃的半导体结构的方法。该方法包括在晶片的第一层上形成调制掺杂硅酸盐玻璃结构的步骤。调制掺杂硅酸盐玻璃结构通过在第一层上沉积至少两层重掺杂硅酸盐玻璃和轻掺杂硅酸盐玻璃的交替层而形成。重掺杂的硅酸盐玻璃和轻掺杂的硅酸盐玻璃层可以包括掺杂有第一掺杂剂和第二掺杂剂的玻璃。第一掺杂剂可以表示例如磷，第二掺杂剂可以表示例如硼。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式