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11. 发明授权

US5933747A Method and structure for an advanced isolation spacer shell 失效
标题翻译：高级隔离隔离壳的方法和结构
公开(公告)号：US5933747A
公开(公告)日：1999-08-03
申请号：US993390
申请日：1997-12-18
申请人： Mark I. Gardner , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Thomas E. Spikes, Jr.
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method and structure are provided for a spacer shell structure which is formed of dielectric materials seletive to one another. The dielectric materials can be configured into a chosen geometric arrangement. The isolation properties of the spacer shell can be scaled to meet a given set of isolation requirements as determined by the size and density of the IGFET devices being isolated. The method to fabricate the novel spacer shell maintains costly fabrication steps at a minimum. The isolation ability of the novel spacer shell preserves the operation integrity of neighboring IGFET devices. Electrical shorts between adjacent devices are prevented. Capacitive coupling between neighboring IGFET structures is likewise minimized.
摘要翻译：提供了一种隔离壳结构的方法和结构，该隔离壳结构由彼此相互连接的电介质材料形成。介电材料可以被配置成所选择的几何布置。间隔壳的隔离性能可以缩放以满足由隔离的IGFET器件的尺寸和密度所确定的给定的隔离要求。制造新型间隔壳的方法至少保持了昂贵的制造步骤。新型间隔壳的隔离能力保持了相邻IGFET器件的操作完整性。防止相邻设备之间的电气短路。相邻IGFET结构之间的电容耦合同样被最小化。

12. 发明授权

US06225201B1 Ultra short transistor channel length dictated by the width of a sidewall spacer 失效
标题翻译：超短晶体管通道长度由侧壁间隔物的宽度决定
公开(公告)号：US06225201B1
公开(公告)日：2001-05-01
申请号：US09433801
申请日：1999-11-03
申请人： Mark I. Gardner , Derrick J. Wristers , Jon D. Cheek , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Derrick J. Wristers , Jon D. Cheek , Thomas E. Spikes, Jr.
IPC分类号： H01L213205
CPC分类号： H01L29/517 , H01L21/0338 , H01L21/28114 , H01L21/28132 , H01L21/2815 , H01L21/28194 , H01L21/31144 , H01L29/6659 , H01L29/66659 , Y10S438/947
摘要： An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length dictated by the width of a sidewall spacer which either embodies a gate conductor for the transistor or is used to pattern an underlying gate conductor. In one embodiment, the sidewall spacers are formed upon and extending laterally from the opposed sidewall surfaces of a sacrificial material. The sidewall surfaces of the sacrificial material are defined by forming the sacrificial material within an opening interposed laterally between vertically extending sidewalls which bound a gate dielectric. An upper portion of the gate dielectric is removed to partially expose the sidewall surfaces arranged at the periphery of the sacrificial material. Polysilicon spacers are formed exclusively upon the sidewall surfaces of the sacrificial material to define a pair of gate conductors having relatively small lateral widths. Portions of the gate dielectric not arranged exclusively beneath the gate conductors may be selectively removed. In another embodiment, sidewall spacers are used to protect select regions of a polysilicon gate material arranged exclusively underneath the spacers from being etched. The sidewall spacers are formed upon and extending laterally from sidewall surfaces arranged at the periphery of an opening which extends through a masking or sacrificial material to an underlying polysilicon gate material. The sidewall spacers are sacrificial in that they are removed from the semiconductor topography after they have served their purpose of masking the underlying polysilicon gate material.
摘要翻译：提供了一种集成电路制造工艺，用于形成具有由侧壁间隔物的宽度所规定的超短沟道长度的晶体管，该侧壁间隔物体现了晶体管的栅极导体或用于对下面的栅极导体进行图案化。在一个实施例中，侧壁间隔件形成在牺牲材料的相对的侧壁表面上并从牺牲材料的相对侧壁表面延伸。牺牲材料的侧壁表面通过在封闭栅极电介质的垂直延伸侧壁之间横向插入的开口内形成牺牲材料来限定。去除栅极电介质的上部以部分地暴露设置在牺牲材料的周边处的侧壁表面。专门在牺牲材料的侧壁表面上形成多晶硅间隔物，以限定具有相对小的横向宽度的一对栅极导体。可以选择性地去除不排列在栅极导体下方的栅极电介质的部分。在另一个实施例中，侧壁间隔件用于保护专门在间隔物下方布置的多晶硅栅极材料的选择区域被蚀刻。侧壁间隔件形成在侧壁表面上并且从侧壁表面延伸出来，该侧壁表面布置在开口的周边，该开口延伸穿过掩模或牺牲材料到下面的多晶硅栅极材料。侧壁间隔物是牺牲的，因为它们已经用于掩盖下面的多晶硅栅极材料的目的，从半导体拓扑图中去除它们。

13. 发明授权

US6140190A Method and structure for elevated source/drain with polished gate electrode insulated gate field effect transistors 失效
标题翻译：具有抛光栅电极绝缘栅场效应晶体管的源/漏源升高的方法和结构
公开(公告)号：US6140190A
公开(公告)日：2000-10-31
申请号：US993388
申请日：1997-12-18
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , Michael P. Duane
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , Michael P. Duane
IPC分类号： H01L21/336 , H01L29/417 , H01L29/49
CPC分类号： H01L29/6659 , H01L29/41775 , H01L29/41783 , H01L29/495 , H01L29/66545
摘要： A method and structure are provided for an IGFET which has elevated source/drain regions and polished gate electrode. The IGFET provides raised doped polysilicon regions between the source/drain areas and subsequent metallization layers. The doped polysilicon regions are scalable. Integration of elevated source/drain regions provides a shallow junction for high performance IGFET design. A refractory metal gate is provided without sacrificing the fabrication advantage of self-aligned techniques. A method to produce an IGFET which incorporates both of the above advantages into a single device, with relatively few process steps, is also provided. Fabricating the gate electrode in this manner will enable metal gate electrodes to be integrated with source/drain structure.
摘要翻译：为具有升高的源极/漏极区域和抛光的栅电极的IGFET提供了一种方法和结构。 IGFET在源极/漏极区域和随后的金属化层之间提供凸起的掺杂多晶硅区域。掺杂多晶硅区域是可扩展的。提升的源极/漏极区域的集成提供了用于高性能IGFET设计的浅结。提供难熔金属栅极，而不牺牲自对准技术的制造优点。还提供了一种产生IGFET的方法，其将上述两个优点并入单个装置，并且具有相对较少的工艺步骤。以这种方式制造栅电极将使金属栅电极与源/漏结构集成。

14. 发明授权

US6140163A Method and apparatus for upper level substrate isolation integrated with bulk silicon 失效
标题翻译：用于与体硅一体化的上层衬底隔离的方法和装置
公开(公告)号：US6140163A
公开(公告)日：2000-10-31
申请号：US893744
申请日：1997-07-11
申请人： Mark I. Gardner , Daniel Kadosh , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Daniel Kadosh , Thomas E. Spikes, Jr.
IPC分类号： H01L21/822 , H01L21/00 , H01L21/84 , H01L27/01 , H01L27/12
CPC分类号： H01L27/0688 , H01L21/8221 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： A high performance semiconductor device structure and method of making the same include a bulk semiconductor substrate and an upper level silicon substrate. The upper level silicon substrate includes a low-K dielectric layer and a silicon substrate layer. The low-K dielectric layer is formed on the bulk semiconductor substrate, the low-K dielectric layer having a dielectric K-value in the range of 2.0-3.8. The silicon substrate layer and low-K dielectric layer are then patterned into the upper level substrate in a first region and the bulk semiconductor substrate is exposed in a second region. A gate oxide layer is formed over the upper level substrate in the first region and over the exposed bulk semiconductor substrate in the second region. Lastly, transistor device formations are formed in the upper level substrate and in the bulk semiconductor substrate.
摘要翻译：高性能半导体器件结构及其制造方法包括体半导体衬底和上层硅衬底。上层硅衬底包括低K电介质层和硅衬底层。低K电介质层形成在体半导体衬底上，低K电介质层的介电K值在2.0-3.8范围内。然后将硅衬底层和低K电介质层在第一区域中被图案化到上层衬底中，并且在第二区域中暴露体半导体衬底。栅极氧化物层形成在第一区域中的上层衬底之上并且在第二区域中的暴露的体半导体衬底之上。最后，晶体管器件形成在上层衬底和体半导体衬底中。

15. 发明授权

US6100204A Method of making ultra thin gate oxide using aluminum oxide 失效
标题翻译：使用氧化铝制造超薄栅极氧化物的方法
公开(公告)号：US6100204A
公开(公告)日：2000-08-08
申请号：US123657
申请日：1998-07-28
申请人： Mark I. Gardner , Mark C. Gilmer , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Mark C. Gilmer , Thomas E. Spikes, Jr.
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L21/469
CPC分类号： H01L21/28185 , H01L29/517 , H01L29/6659 , H01L21/28194
摘要： A transistor and a method of making the same are provided. The method includes the step of forming a gate dielectric layer on the substrate where the gate dielectric layer is composed of an aluminum oxide containing material. A gate electrode is formed on the gate dielectric layer and first and second source/drain regions are formed in the substrate laterally separated to define a channel region beneath the gate electrode. The aluminum oxide containing material may be, for example, Al.sub.2 O.sub.3. Aluminum oxide provides for a gate dielectric with a thin equivalent thickness of oxide in a potentially single crystal form.
摘要翻译：提供晶体管及其制造方法。该方法包括在栅极电介质层由含氧化铝材料构成的基板上形成栅极电介质层的步骤。栅极电极形成在栅极介电层上，并且第一和第二源极/漏极区域形成在衬底中横向分离以限定栅电极下方的沟道区域。含氧化铝的材料可以是例如Al 2 O 3。氧化铝以可能的单晶形式提供具有薄的当量厚度的氧化物的栅极电介质。

16. 发明授权

US6064102A Semiconductor device having gate electrodes with different gate insulators and fabrication thereof 失效
标题翻译：具有栅电极和不同栅极绝缘体的半导体器件及其制造
公开(公告)号：US6064102A
公开(公告)日：2000-05-16
申请号：US992318
申请日：1997-12-17
申请人： Mark I. Gardner , H. Jim Fulford , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , H. Jim Fulford , Thomas E. Spikes, Jr.
IPC分类号： H01L21/8234 , H01L29/76
CPC分类号： H01L21/823462
摘要： A semiconductor device having gate electrodes with different gate insulators and a process for fabricating such device is provided. Consistent with one embodiment of the invention, a semiconductor device is provided in which a first gate insulator is formed over a first region of a substrate. A second gate insulator, different than the first gate insulator, is formed over a second region of the substrate. Finally, one or more gate electrodes are formed over each of the first and second gate insulators. The first gate insulator may, for example, have a permittivity and/or a thickness which is different from that of the second gate insulator. For example, the first gate insulator may have a permittivity greater than 20, and the second gate insulator may have a permittivity less than 10.
摘要翻译：提供了具有不同栅极绝缘体的栅电极和制造这种器件的工艺的半导体器件。根据本发明的一个实施例，提供一种半导体器件，其中在衬底的第一区域上形成第一栅极绝缘体。与第一栅极绝缘体不同的第二栅极绝缘体形成在衬底的第二区域上。最后，在第一和第二栅极绝缘体的每一个上形成一个或多个栅电极。第一栅极绝缘体可以例如具有不同于第二栅极绝缘体的介电常数和/或厚度。例如，第一栅极绝缘体可以具有大于20的介电常数，并且第二栅极绝缘体可以具有小于10的介电常数。

17. 发明授权

US5970375A Semiconductor fabrication employing a local interconnect 失效
标题翻译：采用局部互连的半导体制造
公开(公告)号：US5970375A
公开(公告)日：1999-10-19
申请号：US851086
申请日：1997-05-03
申请人： Mark I. Gardner , Daniel Kadosh , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Daniel Kadosh , Thomas E. Spikes, Jr.
IPC分类号： H01L21/768 , H01L21/336
CPC分类号： H01L21/76895
摘要： An integrated circuit fabrication process is provided in which a sub-level local interconnect is formed between a gate conductor of one transistor and a junction of another transistor. The formation of a sub-level local interconnect allows for higher packing density by removing the local interconnect to a sub-level dielectrically spaced from possibly other local interconnects and from the distal interconnect normally associated with device interconnection. A semiconductor topography is provided which includes a first transistor laterally spaced from a second transistor, the transistors being arranged upon and within the substrate. An interlevel dielectric is deposited across the semiconductor topography. A portion of the interlevel dielectric is removed to form a trench. The trench is then filled with a conductive material to form a local interconnect extending horizontally above a portion of the first transistor and a portion of the second transistor. Portions of the interlevel dielectric and the local interconnect are removed in sequence while retaining the patterned masking layer. Removal of the local interconnect forms vias extending to the gate conductor of one transistor and to a junction of the other transistor, or from the gate conductor of one transistor to a junction of the same transistor. A conductive material may be deposited in these vias to form plugs therein. Further, a capping dielectric layer may be deposited upon the interlevel dielectric and contact regions may be formed which abut the plugs. Therefore, distal interconnect conductive layers may then be formed dielectrically above the local interconnect which are then electrically coupled to the local interconnect through the contact regions.
摘要翻译：提供一种集成电路制造工艺，其中在一个晶体管的栅极导体和另一个晶体管的结之间形成子级局部互连。子级局部互连的形成允许通过将本地互连移除到与可能的其它本地互连以及通常与设备互连相关联的远端互连的介电间隔的子级别来实现更高的堆叠密度。提供半导体形貌，其包括与第二晶体管横向隔开的第一晶体管，晶体管布置在衬底上和衬底内。跨越半导体形貌沉积层间电介质。去除层间电介质的一部分以形成沟槽。然后用导电材料填充沟槽，以形成在第一晶体管的一部分和第二晶体管的一部分上方水平延伸的局部互连。层叠电介质和局部互连的部分在保持图案化掩模层的同时被顺序地去除。去除局部互连形成延伸到一个晶体管的栅极导体和另一个晶体管的结或从一个晶体管的栅极导体到同一晶体管的结的结的通孔。导电材料可以沉积在这些通孔中以在其中形成插塞。此外，可以在层间电介质上沉积覆盖电介质层，并且可以形成接触插塞的接触区域。因此，远端互连导电层然后可以介电地形成在局部互连上方，然后电连接到局部互连通过接触区域。

18. 发明授权

US6074904A Method and structure for isolating semiconductor devices after transistor formation 失效
标题翻译：在晶体管形成之后隔离半导体器件的方法和结构
公开(公告)号：US6074904A
公开(公告)日：2000-06-13
申请号：US63796
申请日：1998-04-21
申请人： Thomas E. Spikes, Jr. , Mark W. Michael , Mark I. Gardner , Robert Dawson
发明人： Thomas E. Spikes, Jr. , Mark W. Michael , Mark I. Gardner , Robert Dawson
IPC分类号： H01L21/762 , H01L21/8238
CPC分类号： H01L21/823878 , H01L21/76237
摘要： A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes a first pair of source/drain regions on either side of a first channel region and a second pair of source/drain regions on either side of a second channel region. One of the first pair of source/drain regions is proximal to one of the second pair of source/drain regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. An isolation trench is formed through the proximal source/drain regions and the trench is filled with a trench dielectric material such that the proximal source/drain regions are electrically isolated whereby the first transistor is electrically isolated from the second transistor.
摘要翻译：一种用于隔离半导体器件的方法，包括提供半导体衬底。半导体衬底包括在第一沟道区的任一侧上的第一对源/漏区和在第二沟道区的任一侧上的第二对源极/漏极区。第一对源极/漏极区域中的一个靠近第二对源极/漏极区域中的一个。第一和第二横向位移的MOS晶体管部分地形成在半导体衬底内。通过近端源极/漏极区域形成隔离沟槽，并且沟槽填充有沟槽电介质材料，使得近端源极/漏极区域被电隔离，由此第一晶体管与第二晶体管电隔离。

19. 发明授权

US6110785A Formulation of high performance transistors using gate trim etch process 失效
标题翻译：使用栅极微调蚀刻工艺制备高性能晶体管
公开(公告)号：US6110785A
公开(公告)日：2000-08-29
申请号：US69533
申请日：1998-04-29
申请人： Thomas E. Spikes, Jr. , Mark I. Gardner , Anthony J. Toprac
发明人： Thomas E. Spikes, Jr. , Mark I. Gardner , Anthony J. Toprac
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66575 , H01L29/7833
摘要： The present invention is directed to a new and improved technique for formation of metal oxide semiconductor field effect transistors. In particular, the method involves formation of an initial gate structure that is wider than the desired final channel length of the completed transistor. Thereafter, an initial heavy-doping step is applied to the drain and source regions of the device. The width of the gate structure is then patterned and etched back to the desired final channel length of the device. A second, light-doping LDD implant is performed to complete the source and drain regions of the finished device.
摘要翻译：本发明涉及用于形成金属氧化物半导体场效应晶体管的新的和改进的技术。特别地，该方法涉及形成比完成的晶体管的期望的最终沟道长度更宽的初始栅极结构。此后，将初始的重掺杂步骤施加到器件的漏极和源极区域。然后将栅极结构的宽度图案化并蚀刻回设备的期望的最终通道长度。执行第二个光掺杂LDD注入以完成成品器件的源极和漏极区域。

20. 发明授权

US6048766A Flash memory device having high permittivity stacked dielectric and fabrication thereof 有权
标题翻译：具有高介电常数堆叠电介质及其制造的闪速存储器件
公开(公告)号：US6048766A
公开(公告)日：2000-04-11
申请号：US172410
申请日：1998-10-14
申请人： Mark I. Gardner , Mark C. Gilmer , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Mark C. Gilmer , Thomas E. Spikes, Jr.
IPC分类号： H01L21/28 , H01L29/423 , H01L29/51 , H01L21/336
CPC分类号： H01L29/516 , H01L21/28273 , H01L29/42324 , H01L29/511 , H01L21/28194
摘要： A memory device having a high performance stacked dielectric sandwiched between two polysilicon plates and method of fabrication thereof is provided. A memory device, in accordance with an embodiment, includes two polysilicon plates and a high permittivity dielectric stack disposed between the two polysilicon plates. The high permittivity dielectric stack includes a relatively high permittivity layer and two relatively low permittivity buffer layers. Each buffer layer is disposed between the relatively high permittivity layer and a respective one of the two polysilicon plates. The high permittivity layer may, for example, be a barium strontium titanate and the buffer layers may each include a layer of silicon nitride adjacent the respective polysilicon plate and a layer of titanium dioxide between the silicon nitride and the barium strontium titanate. The new high performance dielectric layer can, for example, increase the speed and reliability of the memory device as compared to conventional memory devices.
摘要翻译：提供了一种具有夹在两个多晶硅板之间的高性能堆叠电介质的存储器件及其制造方法。根据实施例的存储器件包括两个多晶硅板和设置在两个多晶硅板之间的高介电常数介电堆叠。高介电常数介电堆叠包括相对较高的介电常数层和两个较低的介电常数缓冲层。每个缓冲层设置在相对较高的介电常数层和两个多晶硅板的相应的一个之间。高电容率层可以是例如钛酸锶钡，并且缓冲层可以各自包括邻近相应多晶硅板的氮化硅层和氮化硅和钛酸钡锶钛之间的二氧化钛层。例如，与传统的存储器件相比，新的高性能介电层可以提高存储器件的速度和可靠性。

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