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11. 发明授权

US06287920B1 Method of making multiple threshold voltage integrated of circuit transistors 有权
标题翻译：制作集成电路晶体管的多个阈值电压的方法
公开(公告)号：US06287920B1
公开(公告)日：2001-09-11
申请号：US09640485
申请日：2000-08-16
申请人： Amitava Chatterjee , Mahalingam Nandakumar
发明人： Amitava Chatterjee , Mahalingam Nandakumar
IPC分类号： H01L218236
CPC分类号： H01L21/823412
摘要： A method for forming multiple threshold voltage integrated circuit transistors. Angled pocket type implants (80) are performed to form asymmetric regions (90) and (95). The source and drain regions (120, 121, 122, and 123) are connected such that multiple threshold voltage transistors are formed.
摘要翻译：一种用于形成多个阈值电压集成电路晶体管的方法。进行倾斜袋型植入物（80）以形成不对称区域（90）和（95）。源极和漏极区域（120,121,122和123）被连接成使得形成多个阈值电压晶体管。

12. 发明授权

US06479339B2 Use of a thin nitride spacer in a split gate embedded analog process 有权
公开(公告)号：US06479339B2
公开(公告)日：2002-11-12
申请号：US09967207
申请日：2001-09-28
申请人： Mahalingam Nandakumar , Amitava Chatterjee
发明人： Mahalingam Nandakumar , Amitava Chatterjee
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , H01L21/266 , H01L21/823814
摘要： A mixed voltage CMOS process for high reliability and high performance core transistors and input-output and analog transistors with reduced mask steps. A patterned silicon nitride film 160 is used to selectively mask various implant species during the formation of the LDD regions 180, 220, and the pocket regions 190, 230 of the core transistors 152, 154. The LDD regions 240, 200 of the I/O or analog transistors 156, 158 are simultaneously formed during the process.

13. 发明授权

US08659112B2 Carbon and nitrogen doping for selected PMOS transistor on an integrated circuit 有权
标题翻译：在集成电路上选择PMOS晶体管的碳氮掺杂
公开(公告)号：US08659112B2
公开(公告)日：2014-02-25
申请号：US12967109
申请日：2010-12-14
申请人： Mahalingam Nandakumar , Amitabh Jain
发明人： Mahalingam Nandakumar , Amitabh Jain
IPC分类号： H01L21/70 , H01L27/088 , H01L21/8234
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/28202 , H01L21/823418 , H01L21/823462 , H01L29/1083 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.
摘要翻译：形成包括芯和非芯型PMOS晶体管的集成电路（IC）的方法包括在栅极电介质上形成包括栅电极的非核栅极结构和在栅极电介质上包括栅电极的芯栅极结构。与核心栅极结构的栅极电介质相比，非核心栅极结构的栅极电介质至少为等效氧化物厚度（EOT）的2埃。包括硼的P型轻掺杂漏极（PLDD）注入在衬底中建立源极/漏极延伸区域。 PLDD注入包括将碳和氮选择性共注入到非核栅极结构的源极/漏极延伸区域中。源极和漏极注入形成用于非核和核栅极结构的源极/漏极区，其中源极/漏极区远离它们的源极/漏极延伸区域的非核心和核栅极结构。在源极和漏极之间进行源极/漏极退火。

14. 发明申请

US20090166675A1 STRAIN ENGINEERING IN SEMICONDUCTOR COMPONENTS 审中-公开
标题翻译：半导体器件中的应变工程
公开(公告)号：US20090166675A1
公开(公告)日：2009-07-02
申请号：US12346458
申请日：2008-12-30
申请人： Mahalingam Nandakumar
发明人： Mahalingam Nandakumar
IPC分类号： H01L29/737 , H01L21/265 , H01L21/337
CPC分类号： H01L21/02658 , H01L21/02667
摘要： This disclosure relates to strain engineering to improve the performance of semiconductor components that include a strained region of the semiconductor substrate. The disclosure involves the amorphization of the target region and the recrystallization of the atomic lattice whilst imposing a strain on the region. The region so formed will form a strained lattice, wherein the strain is uniformly distributed throughout the region, and which retains the intrinsic strain even if the source of the mechanical strain is removed. The disclosure includes methods for forming semiconductor substrates having strained regions (such as semiconductor components having a strained channel region) and semiconductor components formed thereby, as well as variations having various properties and advantages.
摘要翻译：本公开涉及应变工程，以改善包括半导体衬底的应变区域的半导体部件的性能。本公开涉及目标区域的非晶化和原子格子的再结晶，同时在该区域上施加应变。这样形成的区域将形成应变格子，其中应变均匀地分布在整个区域中，并且即使去除了机械应变源，其也保留了本征应变。本公开包括用于形成具有应变区域（例如具有应变通道区域的半导体部件）和由其形成的半导体部件的半导体衬底的方法以及具有各种性质和优点的变型。

15. 发明申请

US20090004805A1 Damage Implantation of a Cap Layer 有权
标题翻译：盖层的损伤植入
公开(公告)号：US20090004805A1
公开(公告)日：2009-01-01
申请号：US11771269
申请日：2007-06-29
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L21/336 , H01L23/58
CPC分类号： H01L29/7847 , H01L21/31155 , H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L29/6659
摘要： A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
摘要翻译：一种用于在半导体晶片上制造晶体管的方法包括提供包含栅极堆叠，延伸区域和源极/漏极侧壁的部分晶体管。该方法还包括执行半导体晶片的源极/漏极注入，在半导体晶片上形成覆盖层，并执行源极/漏极退火。此外，该方法包括执行盖层的损伤注入并去除半导体晶片上的覆盖层。

16. 发明授权

US07393787B2 Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therein using a high temperature chemical treatment 有权
标题翻译：使用高温化学处理形成其中具有均匀氮分布的含氮介电层
公开(公告)号：US07393787B2
公开(公告)日：2008-07-01
申请号：US11209140
申请日：2005-08-22
申请人： Hiroaki Niimi , Reima T. Laaksonen , Mahalingam Nandakumar
发明人： Hiroaki Niimi , Reima T. Laaksonen , Mahalingam Nandakumar
IPC分类号： H01L21/302
CPC分类号： H01L27/11 , H01L21/823462 , H01L21/823857 , H01L21/8249
摘要： The present invention provides a method for manufacturing a gate dielectric, a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit. The method for manufacturing the gate dielectric, without limitation, may include forming a nitrided dielectric layer (520) over a substrate (310), the nitrided dielectric layer (520) having a non-uniformity of nitrogen in a bulk thereof, and removing at least a portion of the nitrided dielectric layer (520) using a high temperature chemical treatment, the removing reducing the non-uniformity.
摘要翻译：本发明提供一种栅极电介质的制造方法，半导体器件的制造方法以及集成电路的制造方法。用于制造栅极电介质的方法，但不限于，可以包括在衬底（310）上形成氮化介电层（520），氮化介电层（520）在其主体中具有不均匀的氮，并且在使用高温化学处理的氮化介电层（520）的至少一部分，去除减少不均匀性。

17. 发明授权

US07678637B2 CMOS fabrication process 有权
标题翻译： CMOS制作工艺
公开(公告)号：US07678637B2
公开(公告)日：2010-03-16
申请号：US12209270
申请日：2008-09-12
申请人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
发明人： Mahalingam Nandakumar , Song Zhao , Amitabh Jain
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823814 , H01L29/1087 , H01L29/7847
摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
摘要翻译：对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

18. 发明申请

US20090170277A1 IMPLANT DAMAGE OF LAYER FOR EASY REMOVAL AND REDUCED SILICON RECESS 有权
标题翻译：对于易于去除和减少的硅损伤的层的损伤
公开(公告)号：US20090170277A1
公开(公告)日：2009-07-02
申请号：US12345414
申请日：2008-12-29
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L21/764 , H01L21/302
CPC分类号： H01L21/76254 , H01L21/3086 , H01L21/31111 , H01L21/32139
摘要： A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.
摘要翻译：提供一种用于半导体处理的方法，其中通过离子注入在结构上弱化一个或多个层来帮助去除一层或多层。提供具有形成在其上的一个或多个初级层的半导体衬底，并且在一个或多个初级层上形成二次层。一个或多个离子种类被注入到二次层中，其中结构上弱化了二次层，并且在二级层上形成图案化的光致抗蚀剂层。除去未被图案化光致抗蚀剂层覆盖的二次层和一个或多个初级层的各部分，并进一步除去图案化的光致抗蚀剂层。第二层的至少另一部分被去除，其中次级层的结构弱化增加了次级层的至少另一部分的去除速率。

19. 发明申请

US20060246645A1 A MOS Transistor with a Three-Step Source/Drain Implant 审中-公开
标题翻译：具有三步源/漏植入物的MOS晶体管
公开(公告)号：US20060246645A1
公开(公告)日：2006-11-02
申请号：US11457569
申请日：2006-07-14
申请人： Mahalingam Nandakumar , Seetharaman Sridhar , Mark Rodder
发明人： Mahalingam Nandakumar , Seetharaman Sridhar , Mark Rodder
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7836 , H01L29/6659
摘要： A new MOS transistor is described. The transistor has a source/drain region that comprises 3 portions. Each portion is the result of a separate ion implant step. The combination of the three portions of the source/drain region yields a transistor of superior performance with high drive current, low sub-threshold current and gate-edge leakage.
摘要翻译：描述了新的MOS晶体管。晶体管具有包含3个部分的源极/漏极区域。每个部分是单独的离子注入步骤的结果。源极/漏极区域的三个部分的组合产生具有高驱动电流，低亚阈值电流和栅极边缘泄漏的优异性能的晶体管。

20. 发明申请

US20060024873A1 Method of incorporating stress into a transistor channel by use of a backside layer 有权
标题翻译：通过使用背面层将应力引入晶体管沟道的方法
公开(公告)号：US20060024873A1
公开(公告)日：2006-02-02
申请号：US10902657
申请日：2004-07-28
申请人： Mahalingam Nandakumar , Haowen Bu
发明人： Mahalingam Nandakumar , Haowen Bu
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7833 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located between them. A first stress-inducing layer 190 is placed on a backside of the semiconductor wafer substrate 110 and is subjected to a thermal anneal to cause a stress to form in the channel region 175.
摘要翻译：本发明提供的方法包括在位于半导体晶片衬底110的前侧的栅极结构130附近的半导体晶片衬底110中形成源/漏区170。源极/漏极区170具有位于它们之间的沟道区175。第一应力诱导层190放置在半导体晶片衬底110的背面，并进行热退火以在沟道区175中形成应力。

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