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11. 发明授权

US07551498B2 Implementation of column redundancy for a flash memory with a high write parallelism 有权
标题翻译：实现具有高写入并行性的闪存的列冗余
公开(公告)号：US07551498B2
公开(公告)日：2009-06-23
申请号：US11611452
申请日：2006-12-15
申请人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
发明人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
IPC分类号： G11C7/00
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, an ENABLE_LATCH signal to one of the n groups of m columns to disables corresponding regular senses, and one or r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled. The selected one of the redundant latches activates one of the r redundant senses to access a redundant column.
摘要翻译：冗余存储器阵列具有r列的冗余存储器单元，r冗余感测器和冗余列解码器。冗余地址寄存器存储有缺陷的常规存储单元的地址。在n组r个锁存器中提供冗余锁存器。冗余比较逻辑将缺陷常规存储单元的地址与外部输入地址进行比较。如果比较是真的，提供的是：DISABLE_LOAD信号，用于禁用n列m列中的一个的常规感测，将一个ENABLE_LATCH信号分配给m列的n组中的一组，以禁用相应的常规感官，以及其中之一 r REDO信号到禁用的n个组之一的r个冗余锁存器中的相应一个。所选的一个冗余锁存器激活r个冗余感测之一以访问冗余列。

12. 发明申请

US20060114721A1 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US20060114721A1
公开(公告)日：2006-06-01
申请号：US11123754
申请日：2005-05-05
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre , Andrea Sacco
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C7/04 , G11C16/04 , G11C16/12 , G11C16/30 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop and compensating for temperature variation.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于提供用于存储器单元编程的调节编程电压，用于编程路径电压降的校准编程电压并补偿温度变化。

13. 发明授权

US07242242B2 Fast dynamic low-voltage current mirror with compensated error 有权
标题翻译：具有补偿误差的快速动态低压电流镜
公开(公告)号：US07242242B2
公开(公告)日：2007-07-10
申请号：US11393153
申请日：2006-03-29
申请人： Lorenzo Bedarida , Danut Manea , Mirella Marsella , Andrea Sacco
发明人： Lorenzo Bedarida , Danut Manea , Mirella Marsella , Andrea Sacco
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A current mirror comprising: current source; a first p-channel transistor having a source coupled to operating potential, and a gate and drain coupled to current source; a second p-channel transistor having a source coupled to operating potential, a gate coupled to gate of first p-channel transistor, and a drain; a zero-threshold p-channel transistor having a source coupled to drain of second p-channel transistor, a gate coupled to gate of first p-channel transistor, and a drain; a first n-channel transistor having a source coupled to ground, and a gate and drain coupled to drain of zero-threshold p-channel transistor; a second n-channel transistor having a source coupled to ground, a gate coupled to gate of first n-channel transistor, and a drain; and a zero-threshold n-channel transistor having a source coupled to drain of second n-channel transistor, a gate coupled to gate of first n-channel transistor, and a drain coupled to current-output node.
摘要翻译：电流镜，包括：电流源; 具有耦合到工作电位的源极的第一p沟道晶体管和耦合到电流源的栅极和漏极; 具有耦合到工作电位的源极的第二p沟道晶体管，耦合到第一p沟道晶体管的栅极的栅极和漏极; 零阈值p沟道晶体管，其具有耦合到第二p沟道晶体管的漏极的源极，耦合到第一p沟道晶体管的栅极的栅极和漏极; 第一n沟道晶体管，其具有耦合到地的源极，以及耦合到零阈值p沟道晶体管的漏极的栅极和漏极; 具有耦合到地的源极的第二n沟道晶体管，耦合到第一n沟道晶体管的栅极的栅极和漏极; 以及零阈值n沟道晶体管，其具有耦合到第二n沟道晶体管的漏极的源极，耦合到第一n沟道晶体管的栅极的栅极和耦合到电流输出节点的漏极。

14. 发明授权

US07236050B2 Fast dynamic low-voltage current mirror with compensated error 有权
标题翻译：具有补偿误差的快速动态低压电流镜
公开(公告)号：US07236050B2
公开(公告)日：2007-06-26
申请号：US11393070
申请日：2006-03-29
申请人： Lorenzo Bedarida , Danut Manea , Mirella Marsella , Andrea Sacco
发明人： Lorenzo Bedarida , Danut Manea , Mirella Marsella , Andrea Sacco
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A current mirror comprising: a current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel transistor, and a drain; a first n-channel MOS transistor having a source coupled to ground, and a gate and a drain coupled to the drain of the second p-channel transistor; a zero-threshold n-channel MOS transistor having a drain coupled to a current-output node, a gate coupled to the gate of the first n-channel transistor, and a source; and a second n-channel MOS transistor having a source coupled to ground, and a gate coupled to the gate of the first n-channel transistor and a drain coupled to the source of the zero-threshold n-channel transistor.
摘要翻译：一种电流镜，包括：电流源; 具有耦合到工作电位的源极的第一p沟道MOS晶体管和耦合到电流源的栅极和漏极; 具有耦合到所述工作电位的源极的第二p沟道MOS晶体管，耦合到所述第一p沟道晶体管的栅极的栅极和漏极; 第一n沟道MOS晶体管，其具有耦合到地的源极，以及耦合到第二p沟道晶体管的漏极的栅极和漏极; 具有耦合到电流 - 输出节点的漏极的零阈值n沟道MOS晶体管，耦合到第一n沟道晶体管的栅极的栅极和源极; 以及第二n沟道MOS晶体管，其具有耦合到地的源极，以及耦合到第一n沟道晶体管的栅极的栅极和耦合到零阈值n沟道晶体管的源极的漏极。

15. 发明申请

US20060170489A1 Fast dynamic low-voltage current mirror with compensated error 有权
标题翻译：具有补偿误差的快速动态低压电流镜
公开(公告)号：US20060170489A1
公开(公告)日：2006-08-03
申请号：US11393070
申请日：2006-03-29
申请人： Lorenzo Bedarida , Danut Manea , Mirella Marsella , Andrea Sacco
发明人： Lorenzo Bedarida , Danut Manea , Mirella Marsella , Andrea Sacco
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A current mirror comprising: a current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel transistor, and a drain; a first n-channel MOS transistor having a source coupled to ground, and a gate and a drain coupled to the drain of the second p-channel transistor; a zero-threshold n-channel MOS transistor having a drain coupled to a current-output node, a gate coupled to the gate of the first n-channel transistor, and a source; and a second n-channel MOS transistor having a source coupled to ground, and a gate coupled to the gate of the first n-channel transistor and a drain coupled to the source of the zero-threshold n-channel transistor.
摘要翻译：一种电流镜，包括：电流源; 具有耦合到工作电位的源极的第一p沟道MOS晶体管和耦合到电流源的栅极和漏极; 具有耦合到所述工作电位的源极的第二p沟道MOS晶体管，耦合到所述第一p沟道晶体管的栅极的栅极和漏极; 第一n沟道MOS晶体管，其具有耦合到地的源极，以及耦合到第二p沟道晶体管的漏极的栅极和漏极; 具有耦合到电流 - 输出节点的漏极的零阈值n沟道MOS晶体管，耦合到第一n沟道晶体管的栅极的栅极和源极; 以及第二n沟道MOS晶体管，其具有耦合到地的源极，以及耦合到第一n沟道晶体管的栅极的栅极和耦合到零阈值n沟道晶体管的源极的漏极。

16. 发明授权

US07084699B2 Fast dynamic low-voltage current mirror with compensated error 有权
标题翻译：具有补偿误差的快速动态低压电流镜
公开(公告)号：US07084699B2
公开(公告)日：2006-08-01
申请号：US11102031
申请日：2005-04-07
申请人： Lorenzo Bedarida , Danut Manea , Mirella Marsella , Andrea Sacco
发明人： Lorenzo Bedarida , Danut Manea , Mirella Marsella , Andrea Sacco
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A current mirror comprising: a first current source; a first n-channel MOS transistor having a drain and a gate coupled to said current source and a source coupled to ground; a second n-channel MOS transistor having a drain, a gate coupled to said drain and said gate of said first n-channel MOS transistor, and a source coupled to ground; a third n-channel MOS transistor having a source coupled to said drain of said second n-channel MOS transistor, a gate, and a drain comprising an output-current node; a second current source; a p-channel MOS transistor having a drain coupled to ground, a source coupled to said second current source and said gate of said third n-channel MOS transistor, and a gate coupled to said drain and said gate of said first n-channel MOS transistor.
摘要翻译：一种电流镜，包括：第一电流源; 第一n沟道MOS晶体管，其具有耦合到所述电流源的漏极和栅极以及耦合到地的源极; 具有漏极的第二n沟道MOS晶体管，耦合到所述漏极的栅极和所述第一n沟道MOS晶体管的所述栅极以及耦合到地的源极; 第三n沟道MOS晶体管，具有耦合到所述第二n沟道MOS晶体管的所述漏极的源极，栅极和包括输出电流节点的漏极; 第二个电流源; 具有耦合到地的漏极的p沟道MOS晶体管，耦合到所述第二电流源和所述第三n沟道MOS晶体管的所述栅极的源极，以及耦合到所述第一n沟道MOS晶体管的所述漏极和所述栅极的栅极晶体管。

17. 发明授权

US07301814B2 System and method for avoiding offset in and reducing the footprint of a non-volatile memory 有权
标题翻译：用于避免偏移和减少非易失性存储器的占用空间的系统和方法
公开(公告)号：US07301814B2
公开(公告)日：2007-11-27
申请号：US11126473
申请日：2005-05-11
申请人： Massimiliano Frulio , Riccardo Riva Reggiori , Andrea Sacco , Luca Figini
发明人： Massimiliano Frulio , Riccardo Riva Reggiori , Andrea Sacco , Luca Figini
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/28 , G11C16/3436
摘要： A system and method for avoiding offset in and reducing the footprint of a non-volatile memory that has a plurality of memory bank circuits. Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers. The system includes a reference cell matrix coupled to each of the plurality of memory bank circuits. The reference cell matrix is configured to provide reference cell current for each of the plurality of memory bank circuits.
摘要翻译：一种用于避免偏移并减小具有多个存储器组电路的非易失性存储器的占位面积的系统和方法。每个存储体电路具有耦合到读出放大器，耦合到存储器单元的行和列解码器以及耦合到读出放大器的偏置电路的存储单元。该系统包括耦合到多个存储体电路中的每一个的参考单元矩阵。参考单元矩阵被配置为为多个存储体电路中的每一个提供参考单元电流。

18. 发明授权

US06456150B1 Circuit for biasing a bulk terminal of a MOS transistor 有权
标题翻译：用于偏置MOS晶体管的体积端子的电路
公开(公告)号：US06456150B1
公开(公告)日：2002-09-24
申请号：US09661601
申请日：2000-09-14
申请人： Andrea Sacco , Rino Micheloni , Marco Scotti
发明人： Andrea Sacco , Rino Micheloni , Marco Scotti
IPC分类号： H03K301
CPC分类号： H03K19/00315
摘要： A circuit for biasing the bulk terminal of a first MOS transistor having a first terminal connected to a first line set to a first potential, and a second terminal connected to a second line set to a second potential. The biasing circuit includes a second and a third MOS transistors having first terminals connected respectively to the first line and to the second line, second terminals connected to the bulk terminal of the first MOS transistor, and control terminals connected respectively to the second and to the first line.
摘要翻译：一种用于偏置第一MOS晶体管的体积端子的电路，其具有连接到设置为第一电位的第一线路的第一端子，以及连接到设置为第二电位的第二线路的第二端子。偏置电路包括第二和第三MOS晶体管，其具有分别连接到第一线路和第二线路的第一端子，连接到第一MOS晶体管的体积端子的第二端子和分别连接到第二线路和第二端子的控制端子第一行。

19. 发明授权

US06259632B1 Capacitive compensation circuit for the regulation of the word line reading voltage in non-volatile memories 有权
标题翻译：用于调节非易失性存储器中字线读取电压的电容补偿电路
公开(公告)号：US06259632B1
公开(公告)日：2001-07-10
申请号：US09491475
申请日：2000-01-19
申请人： Osama Khouri , Rino Micheloni , Ilaria Motta , Andrea Sacco , Guido Torelli
发明人： Osama Khouri , Rino Micheloni , Ilaria Motta , Andrea Sacco , Guido Torelli
IPC分类号： G11C1606
CPC分类号： G11C11/5621 , G11C8/14 , G11C16/08 , G11C16/30
摘要： Circuit for the regulation of the word line voltage in a memory, including a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when said one or more word lines are being selected, and charge accumulation means that are selectively connectable with the output of the voltage regulator and suitable to accumulate a compensation charge for a voltage drop that takes place on said regulated voltage upon the selection of said one or more word lines of the memory.
摘要翻译：用于调节存储器中的字线电压的电路，包括适于在选择所述一个或多个字线时产生要提供给存储器的一个或多个字线的输出调节电压的电压调节器，以及电荷累积意味着可以选择性地与电压调节器的输出端连接，并且适合于在选择存储器的所述一个或多个字线时，对在所述调节电压上发生的电压降累积补偿电荷。

20. 发明授权

US07447071B2 Low voltage column decoder sharing a memory array p-well 有权
标题翻译：共享一个存储阵列p-well的低压列解码器
公开(公告)号：US07447071B2
公开(公告)日：2008-11-04
申请号：US11557627
申请日：2006-11-08
申请人： Massimiliano Frulio , Stefano Surico , Andrea Sacco , Davide Manfre
发明人： Massimiliano Frulio , Stefano Surico , Andrea Sacco , Davide Manfre
IPC分类号： G11C11/34
CPC分类号： G11C16/08
摘要： A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias the p-well region and a plurality of high-voltage switches are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders. One or more intermediate-level column decoders are formed as low-voltage selector transistors in the p-well between the first-level column decoder and the last-level column decoder. Each of the intermediate-level column decoders also has a high-voltage switch that is activated during a memory erase mode of operation to provide a high voltage to gate terminals of the intermediate-level column decoders.
摘要翻译：多个存储器子阵列形成在p阱区域中。每个存储器子阵列具有至少一个第一级列解码器，其包括也形成在p阱内的多个低压MOS选择晶体管。最后一级解码器形成在p阱区域外部，并且包括高电压MOS晶体管，以向读出放大器阵列之一提供输出信号。在存储器擦除操作模式期间，提供高电压以偏置p阱区域，并且激活多个高压开关以向第一级列解码器中的选择器晶体管的栅极端提供高电压。在第一级列解码器和最后一级列解码器之间的p阱中形成一个或多个中间级列解码器作为低电压选择晶体管。每个中间级列解码器还具有在存储器擦除操作模式期间激活的高压开关，以向中级列解码器的栅极端提供高电压。

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