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11. 发明授权

US07345943B2 Unclocked eFUSE circuit 失效
标题翻译：不频eFUSE电路
公开(公告)号：US07345943B2
公开(公告)日：2008-03-18
申请号：US11426951
申请日：2006-06-28
申请人： Larry Wissel
发明人： Larry Wissel
IPC分类号： G11C17/18
CPC分类号： G11C17/16
摘要： An unclocked electrically programmable fuse (eFUSE) system includes at least two resistive voltage dividers, one voltage divider including an eFUSE, and a differential amplifier. An output node of at least one of the voltage dividers includes an eFUSE that changes an output voltage based on a state of the eFUSE, and the differential amplifier changes the output voltage into a digital output with no clocking capabilities.
摘要翻译：一个非锁定电可编程保险丝（eFUSE）系统至少包括两个电阻分压器，一个分压器，包括一个eFUSE和一个差分放大器。至少一个分压器的输出节点包括基于eFUSE的状态改变输出电压的eFUSE，并且差分放大器将输出电压改变成不具有时钟能力的数字输出。

12. 发明授权

US07000155B2 Redundancy register architecture for soft-error tolerance and methods of making the same 失效
公开(公告)号：US07000155B2
公开(公告)日：2006-02-14
申请号：US10249574
申请日：2003-04-21
申请人： Jeffery H. Oppold , Michael R. Ouellette , Larry Wissel
发明人： Jeffery H. Oppold , Michael R. Ouellette , Larry Wissel
IPC分类号： G11C29/00
CPC分类号： G11C5/005 , G11C11/4125 , G11C29/787
摘要： A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.

13. 发明授权

US07793239B2 Method and system of modeling leakage 失效
标题翻译：渗漏建模方法和系统
公开(公告)号：US07793239B2
公开(公告)日：2010-09-07
申请号：US11379844
申请日：2006-04-24
申请人： James J. Engel , Susan K. Lichtensteiger , Paul J. Sulva , Larry Wissel
发明人： James J. Engel , Susan K. Lichtensteiger , Paul J. Sulva , Larry Wissel
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method and system of modeling power leakage for a design comprises providing one or more cell libraries comprising parameters for particular device characteristics and providing a module configured to determine of cell leakages of a device for a PVT corner. In determining the cell leakage, the module uses the device characteristics contained in the one or more cell libraries, in combination with one or more components at a PVT for a predetermined application and an amount of devices in a leakage path (Fckt) and a leakage distribution (Fchip). There is no need to recharacterize the one or more cell libraries.
摘要翻译：用于设计功率泄漏建模的方法和系统包括提供一个或多个单元库，其包括用于特定器件特性的参数，并提供被配置为确定用于PVT角的器件的单元泄漏的模块。在确定单元泄漏时，模块使用包含在一个或多个单元库中的器件特性，与PVT中的一个或多个组件结合用于预定应用，以及泄漏路径（Fckt）和泄漏分配（Fchip）。不需要重新定义一个或多个细胞库。

14. 发明申请

US20080002450A1 UNCLOCKED EFUSE CIRCUIT 失效
标题翻译： UNCLOCKED EFUSE电路
公开(公告)号：US20080002450A1
公开(公告)日：2008-01-03
申请号：US11426951
申请日：2006-06-28
申请人： Larry Wissel
发明人： Larry Wissel
IPC分类号： G11C17/00
CPC分类号： G11C17/16
摘要： An unclocked electrically programmable fuse (eFUSE) system includes at least two resistive voltage dividers, one voltage divider including an eFUSE, and a differential amplifier. An output node of at least one of the voltage dividers includes an eFUSE that changes an output voltage based on a state of the eFUSE, and the differential amplifier changes the output voltage into a digital output with no clocking capabilities.
摘要翻译：一个非锁定电可编程保险丝（eFUSE）系统至少包括两个电阻分压器，一个分压器，包括一个eFUSE和一个差分放大器。至少一个分压器的输出节点包括基于eFUSE的状态改变输出电压的eFUSE，并且差分放大器将输出电压改变成不具有时钟能力的数字输出。

15. 发明申请

US20070250797A1 METHOD AND SYSTEM OF MODELING LEAKAGE 失效
标题翻译：泄漏建模方法与系统
公开(公告)号：US20070250797A1
公开(公告)日：2007-10-25
申请号：US11379844
申请日：2006-04-24
申请人： James Engel , Susan Lichtensteiger , Paul Sulva , Larry Wissel
发明人： James Engel , Susan Lichtensteiger , Paul Sulva , Larry Wissel
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： G06F17/5036
摘要： A method and system of modeling power leakage for a design comprises providing one or more cell libraries comprising parameters for particular device characteristics and providing a module configured to determine of cell leakages of a device for a PVT corner. In determining the cell leakage, the module uses the device characteristics contained in the one or more cell libraries, in combination with one or more components at a PVT for a predetermined application and an amount of devices in a leakage path (Fckt) and a leakage distribution (Fchip). There is no need to recharacterize the one or more cell libraries.
摘要翻译：用于设计功率泄漏建模的方法和系统包括提供一个或多个单元库，其包括用于特定器件特性的参数，并提供被配置为确定用于PVT角的器件的单元泄漏的模块。在确定单元泄漏时，模块使用包含在一个或多个单元库中的器件特性，与PVT中的一个或多个组件结合用于预定应用，以及泄漏路径（Fckt）和泄漏分配（Fchip）。不需要重新定义一个或多个细胞库。

16. 发明授权

US06609228B1 Latch clustering for power optimization 失效
标题翻译：锁存聚类功能优化
公开(公告)号：US06609228B1
公开(公告)日：2003-08-19
申请号：US09713571
申请日：2000-11-15
申请人： Paul H. Bergeron , Keith M. Carrig , Alvar A. Dean , Roger P. Gregor , David J. Hathaway , David E. Lackey , Harold E. Reindel , Larry Wissel
发明人： Paul H. Bergeron , Keith M. Carrig , Alvar A. Dean , Roger P. Gregor , David J. Hathaway , David E. Lackey , Harold E. Reindel , Larry Wissel
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , G06F2217/78
摘要： A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.
摘要翻译：时钟优化的方法和结构，包括根据时钟信号要求创建时钟馈电电路的初始放置; 识别所述时钟馈送电路的簇，其中每个簇包括与所述簇内的每个时钟馈送电路连接的不同的时钟信号供应装置; 改变时钟馈电电路和时钟信号供应装置之间的引脚连接，以将选定的时钟馈电电路切换到不同的簇，以减少时钟馈送电路和每个集群内的时钟信号供应装置之间的导线长度; 以及在设计约束内调整时钟馈电电路的位置，以进一步减少电线的长度。

17. 发明授权

US5389836A Branch isolation circuit for cascode voltage switch logic 失效
标题翻译：用于共源共栅电压开关逻辑的分支隔离电路
公开(公告)号：US5389836A
公开(公告)日：1995-02-14
申请号：US72276
申请日：1993-06-04
申请人： Allan R. Bertolet , Albert M. Chu , William R. Griffin , John G. Petrovick, Jr. , Larry Wissel
发明人： Allan R. Bertolet , Albert M. Chu , William R. Griffin , John G. Petrovick, Jr. , Larry Wissel
IPC分类号： H03K19/0944 , H03K19/173 , H03K19/096 , H03K19/017 , H03K19/20
CPC分类号： H03K19/09448 , H03K19/1738
摘要： Cascode voltage switch (CVS) logic circuits include a CMOS logic tree having multiple logic branches and a bipolar, branch isolation transistor. Each logic branch of the logic tree changes state between a logic "1" and a logic "0", with a state change being manifested as a charging or discharging of the logic branch. The bipolar transistor comprises a multiple-emitter bipolar transistor wherein each emitter is electrically coupled to a different logic branch of the CMOS logic tree. A precharge circuit, coupled to the logic tree via the bipolar transistor, provides charge to an output of the CVS circuit prior to operation of said logic tree. The logic branches of the logic tree are charged and discharged substantially independently of one another thereby enhancing speed of the combinatorial logic circuit. Various circuit modifications and generalizations are also discussed.
摘要翻译：串联电压开关（CVS）逻辑电路包括具有多个逻辑支路的CMOS逻辑树和双极型支路隔离晶体管。逻辑树的每个逻辑分支在逻辑“1”和逻辑“0”之间改变状态，状态变化表现为逻辑分支的充电或放电。双极晶体管包括多发射极双极晶体管，其中每个发射极电耦合到CMOS逻辑树的不同逻辑分支。通过双极晶体管耦合到逻辑树的预充电电路在所述逻辑树的操作之前向CVS电路的输出提供电荷。逻辑树的逻辑分支基本上彼此独立地充电和放电，从而提高组合逻辑电路的速度。还讨论了各种电路修改和概括。

18. 发明授权

US07930663B2 Structure for integrated circuit for measuring set-up and hold times for a latch element 有权
标题翻译：用于测量闩锁元件的设置和保持时间的集成电路的结构
公开(公告)号：US07930663B2
公开(公告)日：2011-04-19
申请号：US12111609
申请日：2008-04-29
申请人： Larry Wissel
发明人： Larry Wissel
IPC分类号： G06F17/50
CPC分类号： G11C29/003 , G01R31/31725 , G11C11/41 , G11C29/50
摘要： A design structure for an integrated circuit (IC) includes circuitry for measuring accurately at least one of set-up and hold times of a flip-flop included in the IC design. The circuitry uses data determined at the location of the flip-flop in the IC, and includes a first delay element driven by a first clock and configured to supply a zero-delay value of the first clock to a first flip-flop. The circuitry also includes a second delay element having a selectable delay, the second delay element configured to supply a first delayed version of the first clock to a second flip-flop, wherein an output of the first flip-flop is coupled to an input of the second flip-flop. A third delay element has a selectable delay and is coupled in series with the second delay element to supply a second delayed version of the first clock to a third flip-flop, and an output of the second flip-flop is coupled to an input of the third flip-flop. The second delayed version of the clock signal drives the third flip-flop to monitor the second flip-flop delay, the possible “pass set-up” state, and “pass hold” state outputs are determined for the second flip-flop based on a final test state of the second and third flip-flops.
摘要翻译：集成电路（IC）的设计结构包括用于精确地测量IC设计中包括的触发器的设置和保持时间中的至少一个的电路。电路使用在IC中的触发器位置确定的数据，并且包括由第一时钟驱动并被配置为将第一时钟的零延迟值提供给第一触发器的第一延迟元件。电路还包括具有可选延迟的第二延迟元件，第二延迟元件被配置为将第一时钟的第一延迟版本提供给第二触发器，其中第一触发器的输出耦合到第二个触发器。第三延迟元件具有可选择的延迟并且与第二延迟元件串联耦合以将第一时钟的第二延迟版本提供给第三触发器，并且第二触发器的输出耦合到第三个触发器。时钟信号的第二延迟版本驱动第三触发器以监视第二触发器延迟，可能的“通过建立”状态，并且基于第二触发器确定“通过保持”状态输出第二和第三个触发器的最终测试状态。

19. 发明授权

US07773437B2 Design structure for improved memory column redundancy scheme 失效
标题翻译：改进内存列冗余方案的设计结构
公开(公告)号：US07773437B2
公开(公告)日：2010-08-10
申请号：US12116324
申请日：2008-05-07
申请人： Larry Wissel
发明人： Larry Wissel
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/846 , G11C29/848
摘要： A design structure embodied in machine readable medium used in a design process includes a system for implementing a memory column redundancy scheme. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构包括用于实现存储器列冗余方案的系统。该系统包括具有多个列的核心阵列和冗余列，每个冗余列被配置用于读取或写入用于转向磁芯阵列中的有缺陷的列的信息和电路的位，其中电路包括一个列多路复用器，其导致具有存储器列冗余方案包括一个复用级。

20. 发明申请

US20090067270A1 STRUCTURE FOR IMPROVED MEMORY COLUMN REDUNDANCY SCHEME 失效
标题翻译：改进记忆库冗余方案的结构
公开(公告)号：US20090067270A1
公开(公告)日：2009-03-12
申请号：US12116324
申请日：2008-05-07
申请人： Larry Wissel
发明人： Larry Wissel
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/846 , G11C29/848
摘要： A design structure embodied in machine readable medium used in a design process includes a system for implementing a memory column redundancy scheme. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构包括用于实现存储器列冗余方案的系统。该系统包括具有多个列的核心阵列和冗余列，每个冗余列被配置用于读取或写入用于转向磁芯阵列中的有缺陷的列的信息和电路的位，其中电路包括一个列多路复用器，其导致具有存储器列冗余方案包括一个复用级。

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