会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 15. 发明授权
    • Flat panel display including transceiver circuit for digital interface
    • 平板显示器包括用于数字接口的收发电路
    • US08026891B2
    • 2011-09-27
    • US11450771
    • 2006-06-09
    • Jong-Seon KimJun-Hyung SoukMyung-Ryul ChoiSeung-Woo Lee
    • Jong-Seon KimJun-Hyung SoukMyung-Ryul ChoiSeung-Woo Lee
    • G09G3/36
    • G09G5/006
    • The present invention relates to a digital data transceiver circuit applicable to a flat panel display such as an LCD to be placed between graphic signal generation module and liquid crystal display module or between timing control IC and data driver IC, etc. A digital data transceiver circuit of the present invention has a first current source and a second current source, and the second current source is controlled to supply a current or not depending on the status of the lower bit of input data. A transmitter is connected to a node, on which the first and second current sources combine, and the transmission paths of currents from the two current sources are determined depending on the status of the upper bit of input data. A signal of the transmitter is transmitted through a transmission line, and a termination resistor is connected to the transmission line. A receiver detects output data according to a voltage applied to the termination resistor. The digital data transceiver circuit of the present invention can transmit 2-bit or 3-bit data during one clock period, and it is resistible to the noise better than the voltage transmission method and effective to long distance transmission.
    • 数字数据收发电路技术领域本发明涉及适用于诸如LCD之类的平板显示器的数字数据收发器电路,放置在图形信号发生模块和液晶显示模块之间,或定时控制IC与数据驱动器IC之间。数字数据收发电路 本发明具有第一电流源和第二电流源,并且第二电流源被控制以根据输入数据的较低位的状态来提供电流。 发射机连接到第一和第二电流源组合的节点,并且根据输入数据的较高位的状态确定来自两个电流源的电流的传输路径。 发射机的信号通过传输线传输,终端电阻连接到传输线。 接收机根据施加到终端电阻器的电压来检测输出数据。 本发明的数字数据收发电路可以在一个时钟周期内发送2位或3位数据,并且比电压传输方式更能抵抗噪声,有效地进行长距离传输。
    • 18. 发明授权
    • Thin film transistor array panel and manufacturing method thereof
    • 薄膜晶体管阵列面板及其制造方法
    • US07742118B2
    • 2010-06-22
    • US11690563
    • 2007-03-23
    • Jun-Hyung SoukJeong-Young LeeJong-Soo YoonKwon-Young ChoiBum-Ki Baek
    • Jun-Hyung SoukJeong-Young LeeJong-Soo YoonKwon-Young ChoiBum-Ki Baek
    • G02F1/136
    • G02F1/13458G02F1/136227G02F1/136286H01L27/12H01L27/124H01L27/1288
    • A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
    • 提供一种制造薄膜晶体管阵列面板的方法,该方法包括:在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂,比所述第一部分更厚且位于所述漏极上的第二部分,以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模,将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。
    • 19. 发明授权
    • Thin film transistor array panel and manufacturing method thereof
    • 薄膜晶体管阵列面板及其制造方法
    • US07403240B2
    • 2008-07-22
    • US11741470
    • 2007-04-27
    • Jun-Hyung SoukJeong-Young LeeJong-Soo YoonKwon-Young ChoiBum-Ki Baek
    • Jun-Hyung SoukJeong-Young LeeJong-Soo YoonKwon-Young ChoiBum-Ki Baek
    • G02F1/136G02F1/1335
    • G02F1/13458G02F1/136227G02F1/136286H01L27/12H01L27/124H01L27/1288
    • A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
    • 提供一种制造薄膜晶体管阵列面板的方法,该方法包括:在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂,比所述第一部分更厚且位于所述漏极上的第二部分,以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模,将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。
    • 20. 发明申请
    • Thin Film Transistor Array Panel And Manufacturing Method Thereof
    • 薄膜晶体管阵列面板及其制造方法
    • US20070190706A1
    • 2007-08-16
    • US11690563
    • 2007-03-23
    • Jun-Hyung SoukJeong-Young LeeJong-Soo YoonKwon-Young ChoiBum-Ki Baek
    • Jun-Hyung SoukJeong-Young LeeJong-Soo YoonKwon-Young ChoiBum-Ki Baek
    • H01L21/84
    • G02F1/13458G02F1/136227G02F1/136286H01L27/12H01L27/124H01L27/1288
    • A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
    • 提供一种制造薄膜晶体管阵列面板的方法,该方法包括:在绝缘基板上形成栅极线; 形成栅极绝缘层; 形成半导体层; 形成包括数据线和漏电极的数据导电层; 沉积钝化层; 形成包括位于所述栅极线的端部的第一部分的光致抗蚀剂,比所述第一部分更厚且位于所述漏极上的第二部分,以及比所述第二部分更厚的第三部分; 通过使用光致抗蚀剂作为蚀刻掩模,将光致抗蚀剂的第二部分下的钝化层的一部分暴露在光致抗蚀剂的第一部分下方的栅绝缘层的一部分; 形成分别露出所述漏电极和所述栅极线的端部的第一和第二接触孔; 以及通过所述第一接触孔形成连接到所述漏电极的像素电极。