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11. 发明申请

US20090077432A1 Semiconductor Memory Device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20090077432A1
公开(公告)日：2009-03-19
申请号：US12273270
申请日：2008-11-18
申请人： Toshikazu Nakamura , Akira Kikutake , Kuninori Kawabata , Yasuhiro Onishi , Satoshi Eto
发明人： Toshikazu Nakamura , Akira Kikutake , Kuninori Kawabata , Yasuhiro Onishi , Satoshi Eto
IPC分类号： G06F11/00 , G11C29/04 , G06F11/07
CPC分类号： G11C29/42 , G11C11/41
摘要： Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1, an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.
摘要翻译：公开了一种半导体存储器件，其能够任意地设定检验动作时的误差修正量的上限。半导体存储器件具有计数器，寄存器和比较电路。计数器对错误更正次数进行计数。当外部输入上限设定信号（在图1所示的情况下为外部上限获取信号）以改变误差修正次数的上限时，该寄存器改变上限值。比较电路将误差校正次数与改变的上限进行比较。

12. 发明授权

US07467337B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07467337B2
公开(公告)日：2008-12-16
申请号：US11102715
申请日：2005-04-11
申请人： Toshikazu Nakamura , Akira Kikutake , Kuninori Kawabata , Yasuhiro Onishi , Satoshi Eto
发明人： Toshikazu Nakamura , Akira Kikutake , Kuninori Kawabata , Yasuhiro Onishi , Satoshi Eto
IPC分类号： G06F11/00
CPC分类号： G11C29/42 , G11C11/41
摘要： Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.
摘要翻译：公开了一种半导体存储器件，其能够任意地设定检验动作时的误差修正量的上限。半导体存储器件具有计数器，寄存器和比较电路。计数器对错误更正次数进行计数。当外部输入上限设定信号以改变误差修正次数的上限时，寄存器改变上限值。比较电路将误差校正次数与改变的上限进行比较。

13. 发明申请

US20060156192A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20060156192A1
公开(公告)日：2006-07-13
申请号：US11102715
申请日：2005-04-11
申请人： Toshikazu Nakamura , Akira Kikutake , Kuninori Kawabata , Yasuhiro Onishi , Satoshi Eto
发明人： Toshikazu Nakamura , Akira Kikutake , Kuninori Kawabata , Yasuhiro Onishi , Satoshi Eto
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G11C11/41
摘要： Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1, an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.
摘要翻译：公开了一种半导体存储器件，其能够任意地设定检验动作时的误差修正量的上限。半导体存储器件具有计数器，寄存器和比较电路。计数器对错误更正次数进行计数。当外部输入上限设定信号（在图1 所示的情况下为外部上限提取信号）时，该寄存器改变数量的上限错误更正，更改上限。比较电路将误差校正次数与改变的上限进行比较。

14. 发明申请

US20060236206A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060236206A1
公开(公告)日：2006-10-19
申请号：US11270533
申请日：2005-11-10
申请人： Shuzo Otsuka , Kuninori Kawabata , Toshikazu Nakamura , Akira Kikutake
发明人： Shuzo Otsuka , Kuninori Kawabata , Toshikazu Nakamura , Akira Kikutake
IPC分类号： G11C29/00
CPC分类号： G06F11/1032 , G11C7/1006 , G11C7/1027
摘要： In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a code for error correction and are written in memory cells in the leading write cycle in a burst write operation. The set of parity bits written in memory cells in the leading write cycle is updated in the final write cycle on the basis of the portion of the set of data bits and/or the set of parity bits, and another set of data bits required to be written in the final write cycle in the memory cells at the address at which the above portion is written in the leading write cycle.
摘要翻译：在具有纠错功能的半导体存储器件中，保持一组数据位的一部分和基于该数据位组的一组奇偶校验位，其中数据位集合和奇偶校验位构成用于纠错的代码，并且在突发写入操作中以前导写入周期写入存储器单元。基于数据位组和/或奇偶校验位集合的部分，在最终写入周期中更新写入存储器单元中的前导写周期中的奇偶校验位集合，以及另一组数据位在上一部分写入前导写周期的地址处的存储单元中写入最终写周期。

15. 发明授权

US07827463B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07827463B2
公开(公告)日：2010-11-02
申请号：US11270533
申请日：2005-11-10
申请人： Shuzo Otsuka , Kuninori Kawabata , Toshikazu Nakamura , Akira Kikutake
发明人： Shuzo Otsuka , Kuninori Kawabata , Toshikazu Nakamura , Akira Kikutake
IPC分类号： H03M13/00
CPC分类号： G06F11/1032 , G11C7/1006 , G11C7/1027
摘要： In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a code for error correction and are written in memory cells in the leading write cycle in a burst write operation. The set of parity bits written in memory cells in the leading write cycle is updated in the final write cycle on the basis of the portion of the set of data bits and/or the set of parity bits, and another set of data bits required to be written in the final write cycle in the memory cells at the address at which the above portion is written in the leading write cycle.
摘要翻译：在具有纠错功能的半导体存储器件中，保持一组数据位的一部分和基于该数据位组的一组奇偶校验位，其中数据位集合和奇偶校验位构成用于纠错的代码，并且在突发写入操作中以前导写入周期写入存储器单元。基于数据位组和/或奇偶校验位集合的部分，在最终写入周期中更新写入存储器单元中的前导写周期中的奇偶校验位集合，以及另一组数据位在上一部分写入前导写周期的地址处的存储单元中写入最终写周期。

16. 发明授权

US07307885B2 Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit 有权
标题翻译：配有参考电池和负载平衡电路的多值非易失性半导体存储器件
公开(公告)号：US07307885B2
公开(公告)日：2007-12-11
申请号：US11063999
申请日：2005-02-24
申请人： Toshimi Ikeda , Atsushi Hatakeyama , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Toshimi Ikeda , Atsushi Hatakeyama , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C7/14 , G11C2207/002
摘要： A nonvolatile semiconductor memory device includes a plurality of memory cells holding memory cell information, a plurality of bit lines connected to the plurality of memory cells, the plurality of bit lines including a first bit line conected to a selected one of the plurality of memory cells and a plurality of second bit lines connected to non-selected memory cells, a plurality of reference cells supplying different reference currents respectively, and a read-out circuit, wherein, when reading the memory cell information, the read-out circuit is coupled to the first bit line connected to the selected memory cell and coupled to one of the plurality of reference cells through one of the plurality of second bit lines connected to the non-selected memory cells.
摘要翻译：非易失性半导体存储器件包括保持存储单元信息的多个存储器单元，连接到多个存储器单元的多个位线，多个位线包括与多个存储器单元中选择的一个存储单元相连的第一位线以及连接到未选择的存储器单元的多个第二位线，分别提供不同参考电流的多个参考单元和读出电路，其中当读取存储单元信息时，读出电路耦合到所述第一位线连接到所选择的存储器单元，并且通过连接到所述未选择的存储器单元的所述多个第二位线之一耦合到所述多个参考单元中的一个。

17. 发明授权

US07075834B2 Semiconductor integrated circuit device 失效
公开(公告)号：US07075834B2
公开(公告)日：2006-07-11
申请号：US09994610
申请日：2001-11-28
申请人： Kuninori Kawabata , Akira Kikutake , Shinichiro Shiratake
发明人： Kuninori Kawabata , Akira Kikutake , Shinichiro Shiratake
IPC分类号： G11C7/00 , G11C7/02 , G11C7/10
CPC分类号： G11C29/12 , G11C7/1048 , G11C11/4096
摘要： A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mode in which the signal lines are not precharged.

18. 发明申请

US20060133166A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20060133166A1
公开(公告)日：2006-06-22
申请号：US11155731
申请日：2005-06-20
申请人： Akira Kikutake , Yasuhiro Onishi , Kuninori Kawabata , Junichi Sasaki , Toshiya Miyo
发明人： Akira Kikutake , Yasuhiro Onishi , Kuninori Kawabata , Junichi Sasaki , Toshiya Miyo
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G06F11/1032 , G11C11/401 , G11C29/50016 , G11C29/52 , G11C2029/0409
摘要： Regular data inputted/outputted to/from external terminals is read/written to/from a regular cell array, and parity data is read/written from/to a parity cell array. Since the parity data is generated by a parity generation circuit, it is difficult to write a desired pattern to the parity cell array. The regular data and the parity data are exchanged with each other by a switch circuit, so that the regular data can be written to the parity cell array and the parity data can be written to the regular cell array. This enables the write of desired data to the parity cell array. A test of the parity data can be easily conducted. In particular, a leakage test or the like between memory cells can be easily conducted.
摘要翻译：向/从外部端子输入/输出的常规数据被读取/写入常规单元阵列，并且从奇偶校验单元阵列读取/写入奇偶校验数据。由于奇偶校验数据由奇偶产生电路产生，因此难以将奇偶校验单元阵列所需的模式写入。常规数据和奇偶校验数据通过开关电路彼此交换，使得常规数据可以写入奇偶校验单元阵列，并且奇偶校验数据可以写入正常单元阵列。这使得能够将所需数据写入奇偶校验单元阵列。可以容易地进行奇偶校验数据的测试。特别地，可以容易地进行存储单元之间的泄漏测试等。

19. 发明申请

US20050185465A1 Memory device 审中-公开
标题翻译：内存设备
公开(公告)号：US20050185465A1
公开(公告)日：2005-08-25
申请号：US11110700
申请日：2005-04-21
申请人： Nobutaka Taniguchi , Atsushi Hatakeyama , Toshimi Ikeda , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Nobutaka Taniguchi , Atsushi Hatakeyama , Toshimi Ikeda , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C8/12 , G11C11/34 , G11C16/26
CPC分类号： G11C16/26 , G11C8/12
摘要： A memory device includes plural banks (BNKA, BNKB, BNKC, and BNKD), and each of the banks includes a plural memory cells storing data and plural bit lines reading data from the plural memory cells. Bit line lengths of all of the plural banks are equal.
摘要翻译：存储器件包括多个存储体（BNKA，BNKB，BNKC和BNKD），并且每个存储体包括存储数据的多个存储单元和从多个存储单元读取数据的多个位线。所有多个组的位线长度相等。

20. 发明申请

US20050141306A1 Memory device 失效
标题翻译：内存设备
公开(公告)号：US20050141306A1
公开(公告)日：2005-06-30
申请号：US11069940
申请日：2005-03-03
申请人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C5/06 , G11C16/06 , G11C16/28
CPC分类号： G11C16/28
摘要： A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.
摘要翻译：存储器件具有用于连接到存储单元的数据线（DATA-BUS），用于参考的参考线（Reference-BUS），预充电电路（101），负载电路（102）和放大器电路（103））。预充电电路连接到数据线和参考线，并配置为对数据线和参考线进行预充电。负载电路连接到数据线和参考线，并配置为向数据线施加第一恒定电流，并将比第一恒定电流小的第二恒定电流施加到参考线。放大电路连接到数据线和参考线，并被配置为放大数据线与参考线之间的差分电压。

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