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11. 发明授权

US6121085A Method of fabricating contact openings for dynamic random-access memory 失效
标题翻译：制造用于动态随机存取存储器的接触孔的方法
公开(公告)号：US6121085A
公开(公告)日：2000-09-19
申请号：US9508
申请日：1998-01-20
申请人： Chia-Wen Liang , Sun-Chieh Chien , Der-Yuan Wu , Jason Jenq
发明人： Chia-Wen Liang , Sun-Chieh Chien , Der-Yuan Wu , Jason Jenq
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10852
摘要： A method of making contact openings for memory cell units of DRAM IC devices is disclosed. The contact opening is used to connect the cell transistor source/drain terminal to the storage capacitor electrode located substantially above. The method includes the step of first patterning the initial opening in a shielding layer for the contact opening. The diameter of the initial opening is then reduced by the formation of sidewall spacers in initial opening. The initial opening in the shielding layer is then used to implement the etching for the formation of the contact opening. Due to reduced size of the contact opening, short-circuiting situations arising between the via formed in the contact opening and the bit lines next to the via as a result of misalignment in the process of fabrication can be reduced, thereby improving the device fabrication yield rates.
摘要翻译：公开了一种制造DRAM IC器件的存储单元的接触开口的方法。接触开口用于将单元晶体管源极/漏极端子连接到大致位于上方的存储电容器电极。该方法包括首先在接触开口的屏蔽层中构图初始开口的步骤。然后通过在初始开口中形成侧壁间隔来减小初始开口的直径。然后使用屏蔽层中的初始开口来实现用于形成接触开口的蚀刻。由于接触开口的尺寸减小，可以减少在制造工艺中由于在接触开口中形成的通孔与通孔旁边的位线之间产生的短路情况，从而提高器件的制造成品率价格。

12. 发明授权

US6080619A Method for manufacturing DRAM capacitor 失效
标题翻译：制造DRAM电容的方法
公开(公告)号：US6080619A
公开(公告)日：2000-06-27
申请号：US85903
申请日：1998-05-27
申请人： Sun-Chieh Chien , King-Lung Wu , Chuan-Fu Wang , Jason Jenq
发明人： Sun-Chieh Chien , King-Lung Wu , Chuan-Fu Wang , Jason Jenq
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/90
摘要： A method for manufacturing a DRAM capacitor is provided to form a lower electrode with a cylindrical profile by using a first stage and a second stage. The stages provide different etching rates in various situations. The invention uses the stages to allow the part of the second polysilicon layer between the capacitors to be completely etched and prevent the other part of the second polysilicon layer serving as a lower electrode from over-etching. The invention provides an easier process of forming a cylindrical capacitor with a larger surface.
摘要翻译：提供一种用于制造DRAM电容器的方法，以通过使用第一级和第二级形成具有圆柱形轮廓的下电极。这些阶段在各种情况下提供不同的蚀刻速率。本发明使用这些阶段来允许电容器之间的第二多晶硅层的一部分被完全蚀刻，并且防止用作下部电极的第二多晶硅层的另一部分过度蚀刻。本发明提供了形成具有更大表面的圆柱形电容器的更容易的工艺。

13. 发明授权

US5989997A Method for forming dual damascene structure 失效
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US5989997A
公开(公告)日：1999-11-23
申请号：US61659
申请日：1998-04-17
申请人： Benjamin Szu-Min Lin , Jason Jenq
发明人： Benjamin Szu-Min Lin , Jason Jenq
IPC分类号： H01L21/768 , H01L21/314
CPC分类号： H01L21/76808 , Y10S438/948
摘要： A method for forming dual damascene metallic structure that utilizes the formation of a protective photoresist layer at the bottom of a vertical window to prevent damages to a device region in the substrate when subsequent etching operation is carried out to form a horizontal trench pattern. The protective photoresist layer at the bottom of the vertical window is formed by irradiating the photoresist layer with a dose of radiation having energy level insufficient to chemically dissociate the photoactive molecules of the photoresist layer near the bottom of the vertical window.
摘要翻译：一种用于形成双镶嵌金属结构的方法，其利用在垂直窗口的底部形成保护光致抗蚀剂层，以防止当进行后续蚀刻操作以形成水平沟槽图案时对基板中的器件区域的损坏。垂直窗口底部的保护光致抗蚀剂层是通过用能量水平不足以化学解离靠近垂直窗口底部的光致抗蚀剂层的光活性分子的辐射照射光致抗蚀剂层而形成的。

14. 发明授权

US5924007A Method for improving the planarization of inter-poly dielectric 失效
标题翻译：改进多晶硅电介质平面化的方法
公开(公告)号：US5924007A
公开(公告)日：1999-07-13
申请号：US910999
申请日：1997-08-14
申请人： Chia-Wen Liang , Jason Jenq , Chuan-Fu Wang , Sun-Chieh Chien
发明人： Chia-Wen Liang , Jason Jenq , Chuan-Fu Wang , Sun-Chieh Chien
IPC分类号： H01L21/321 , H01L21/469
CPC分类号： H01L21/321
摘要： A method of improving the planarization of inter-poly dielectric layers. On a semiconductor device on which a poly-silicon layer is formed, by using atmosphere chemical vapor deposition, an undoped inter-poly dielectric layer is formed. A doped inter-poly dielectric layer is formed on the undoped inter-poly dielectric layer. Under a high temperature, reflow and etching back operations are performed for the doped inter-poly dielectric layer. Before a second poly-silicon layer is formed, a rapid thermal process is performed.
摘要翻译：一种改善多晶硅介电层平坦化的方法。在形成多晶硅层的半导体器件上，通过使用气氛化学气相沉积，形成未掺杂的多晶硅间介质层。在未掺杂的多晶硅间介质层上形成掺杂的多晶硅介电层。在高温下，对掺杂的多晶硅介电层进行回流和回蚀作业。在形成第二多晶硅层之前，进行快速热处理。

15. 发明授权

US5872055A Method for fabricating polysilicon conducting wires 失效
标题翻译：制造多晶硅导线的方法
公开(公告)号：US5872055A
公开(公告)日：1999-02-16
申请号：US768971
申请日：1996-12-18
申请人： Jason Jenq , Sun-Chieh Chien
发明人： Jason Jenq , Sun-Chieh Chien
IPC分类号： H01L21/3213 , H01L21/768 , H01L21/306 , H01L21/311
CPC分类号： H01L21/32139 , H01L21/32134 , H01L21/76885
摘要： A manufacturing method of fabricating a polysilicon conductive wire suitable for an integrated circuit and which can avoid pattern transfer errors caused by reflection of ultraviolet light during photolithographic processing and that results in constriction in width or the bottlenecking effect in part of the conductive wore. A polysilicon layer is formed above a semiconductor substrate having a preformed device. A cap insulting layer is formed above the polysilicon layer. A micro-roughness structure is formed on the surface of the cap insulating layer. A photoresist layer is coated over the micro-roughened surface of the cap insulating layer. A pattern is transferred onto the photoresist layer by selective light exposure followed by the removal of unexposed photoresist. Then the cap insulating layer and the polysilicon layer are etched in sequence in regions not covered by photoresist. The residual photoresist is then removed to leave behind a polysilicon conductive wire.
摘要翻译：一种制造适用于集成电路的多晶硅导线的制造方法，其可以避免在光刻处理期间由紫外光的反射引起的图案转移误差，并且导致部分导电磨损的宽度缩窄或瓶颈效应。在具有预成型器件的半导体衬底之上形成多晶硅层。在多晶硅层上方形成帽绝缘层。在帽绝缘层的表面上形成微粗糙结构。将光致抗蚀剂层涂覆在帽绝缘层的微粗糙表面上。通过选择性曝光然后去除未曝光的光致抗蚀剂将图案转印到光致抗蚀剂层上。然后在未被光致抗蚀剂覆盖的区域中依次蚀刻帽绝缘层和多晶硅层。然后去除剩余光致抗蚀剂留下多晶硅导电线。

16. 发明授权

US6017788A Method of fabricating bit line 失效
标题翻译：位线的制作方法
公开(公告)号：US6017788A
公开(公告)日：2000-01-25
申请号：US941085
申请日：1997-09-30
申请人： Jason Jenq
发明人： Jason Jenq
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10885 , H01L27/10888 , H01L27/10852 , H01L28/84
摘要： A method of fabricating a bit line comprises first that a semiconductor substrate is provided. The substrate comprises source/drain regions and a semiconductor structure. Over the substrate, an oxide layer conformal to the semiconductor substrate and a BPSG layer are formed. A contact window is formed and exposes the source/drain regions in the substrate. A polysilicon layer is formed within the contact window and connects the source/drain regions. A titanium silicide (TiSi.sub.2) is formed and covers the polysilicon layer. A titanium nitride layer is formed and covers the titanium silicide layer. One of the characteristics of the invention is that a titanium silicide layer, a titanium nitride layer, and a polysilicon layer replaces the conventional tungsten silicide and the polysilicon layer to form a bit line. Therefore, the contact resistance of the bit line is reduced effectively. In addition, the titanium nitride layer can be used as a bottom anti-reflection layer to avoid the necking phenomenon while coating photoresist. Moreover, the titanium nitride layer also prevents the formation of cracking during the subsequent rapid thermal process.
摘要翻译：首先制造位线的方法包括首先提供半导体衬底。衬底包括源极/漏极区域和半导体结构。在衬底上形成与半导体衬底保形的氧化物层和BPSG层。形成接触窗口并暴露衬底中的源极/漏极区域。在接触窗内形成多晶硅层，并连接源/漏区。形成硅化钛（TiSi 2）并覆盖多晶硅层。形成氮化钛层并覆盖硅化钛层。本发明的特征之一是硅化钛层，氮化钛层和多晶硅层取代了常规的硅化钨和多晶硅层以形成位线。因此，有效地降低了位线的接触电阻。此外，氮化钛层可以用作底部防反射层，以避免涂覆光致抗蚀剂时的颈缩现象。此外，氮化钛层还防止在随后的快速热处理期间形成裂纹。

17. 发明授权

US5981330A Process for fabricating bitlines 失效
标题翻译：制造位线的工艺
公开(公告)号：US5981330A
公开(公告)日：1999-11-09
申请号：US34792
申请日：1998-03-03
申请人： Jason Jenq
发明人： Jason Jenq
IPC分类号： H01L21/02 , H01L21/60 , H01L21/8242
CPC分类号： H01L27/10852 , H01L21/76897 , H01L28/82
摘要： A process for fabricating bitlines for DRAM devices having improved bitline electrical contact is disclosed. Good electrical connection for the bitline in its contact opening is secured by forming a contact interface utilizing titanium silicide. The process includes first forming contact openings revealing the source/drain regions of the transistor of the cell units followed by the formation of a polysilicon layer filling into the openings and contacting the revealed surface of the transistor source/drain regions. A tungsten silicide layer then covers the polysilicon layer, with a titanium layer further covering the tungsten silicide layer, and the polysilicon layer in the contact opening exposed out of coverage by the tungsten silicide layer due to insufficient step coverage of the tungsten silicide layer in the openings. A titanium nitride layer then covers the titanium layer, with a titanium silicide layer interfacing between the polysilicon layer and the tungsten silicide filled inside the openings.
摘要翻译：公开了一种用于制造具有改进的位线电接触的DRAM器件的位线的工艺。通过使用钛硅化物形成接触界面来确保接触开口中位线的良好电连接。该工艺包括首先形成露出电池单元的晶体管的源极/漏极区的接触开口，随后形成填充到开口中的多晶硅层，并与晶体管源/漏区的透露表面接触。硅化钨层然后覆盖多晶硅层，其中钛层进一步覆盖硅化钨层，并且接触开口中的多晶硅层由于硅化钨层的覆盖不充分而暴露于硅化钨层的覆盖范围内开口然后，氮化钛层覆盖钛层，硅化钛层在填充在开口内部的多晶硅层和硅化钨之间进行界面连接。

18. 发明授权

US5937307A Process for fabricating DRAM capacitor 失效
标题翻译：制造DRAM电容器的工艺
公开(公告)号：US5937307A
公开(公告)日：1999-08-10
申请号：US041526
申请日：1998-03-12
申请人： Jason Jenq , Der-Yuan Wu
发明人： Jason Jenq , Der-Yuan Wu
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L28/84
摘要： A process of fabricating the storage capacitor of a DRAM memory IC device having increased electrode surface area is disclosed. The hemispherical-grain silicon layer used to effect the area increase does not suffer stripping-off during the process of removal of its native oxide. The prevention of the stripping-off is achieved by the employment of a amorphous silicon layer underlying the hemispherical-grain silicon layer. The amorphous silicon layer improves the adhesiveness of the hemispherical-grain silicon layer, thereby preventing its stripping-off.
摘要翻译：公开了一种制造具有增加的电极表面积的DRAM存储器IC器件的存储电容器的工艺。用于实现面积增加的半球形硅层在去除其天然氧化物的过程中不会被剥离。通过使用半球形硅层下面的非晶硅层来实现剥离的防止。非晶硅层改善了半球形硅层的粘附性，从而防止其剥离。

19. 发明授权

US5893751A Self-aligned silicide manufacturing method 失效
标题翻译：自对准硅化物制造方法
公开(公告)号：US5893751A
公开(公告)日：1999-04-13
申请号：US736939
申请日：1996-10-25
申请人： Jason Jenq , Tung-Po Chen
发明人： Jason Jenq , Tung-Po Chen
IPC分类号： H01L21/285 , H01L21/44
CPC分类号： H01L21/28518
摘要： An improved self-aligned silicide manufacturing method in which prior to the formation of a heat resistant metallic layer on top of a silicon substrate, a treatment of exposed surfaces of a gate terminal and source/drain diffusion regions is performed to increase surface roughness enabling an increase in crystallization nucleus number, as well as lowering crystallization temperature.
摘要翻译：一种改进的自对准硅化物制造方法，其中在硅衬底顶部形成耐热金属层之前，执行对栅极端子和源极/漏极扩散区域的暴露表面的处理，以增加表面粗糙度，从而能够结晶核数增加，结晶温度降低。

20. 发明授权

US5874334A Method for fabricating DRAM capacitor 失效
标题翻译：制造DRAM电容的方法
公开(公告)号：US5874334A
公开(公告)日：1999-02-23
申请号：US8900
申请日：1998-01-20
申请人： Jason Jenq , Sun-Chieh Chien
发明人： Jason Jenq , Sun-Chieh Chien
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/40
摘要： A method for fabricating a DRAM capacitor comprising the steps of forming silicon nitride spacers twice, not only serving as etching stop layer in a self-aligned contact etching process, but also used as a protective layer for the bit line and gate electrode in an etching operation. In another aspect, using silicon nitride spacers has the advantage of being capable of increasing the width of a contact opening. Hence, a contact opening having a smaller height to width ratio can be produced. Furthermore, the lower electrode of the capacitor in this invention is a pillar-shaped structure, and together with the formation of a hemispherical grained silicon layer over the lower electrode, the surface area of the capacitor can be greatly increased. Moreover, a dielectric layer having a high dielectric constant can be used; hence, a capacitor with sufficient capacitance can be provided although the surface area of the storage capacitor is reduced.
摘要翻译：一种用于制造DRAM电容器的方法，包括以下步骤：形成氮化硅间隔物两次，不仅用作自对准接触蚀刻工艺中的蚀刻停止层，而且还用作蚀刻中的位线和栅电极的保护层操作。在另一方面，使用氮化硅间隔物具有能够增加接触开口的宽度的优点。因此，可以制造具有较小高度与宽度比的接触开口。此外，本发明的电容器的下部电极为柱状结构，并且在下部电极上形成半球状的硅层，能够大幅提高电容器的表面积。此外，可以使用具有高介电常数的介电层; 因此，尽管存储电容器的表面积减小，但是可以提供具有足够电容的电容器。

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