专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20090315878A1 PHASE COMPARATOR, AND CLOCK GENERATION CIRCUIT, IMAGE DISPLAY DEVICE, AND REPRODUCTION SIGNAL PROCESSOR EACH USING THE SAME 失效
标题翻译：相位比较器和时钟发生电路，图像显示装置和使用它的再现信号处理器
公开(公告)号：US20090315878A1
公开(公告)日：2009-12-24
申请号：US12439966
申请日：2008-07-08
申请人： Kouji Okamoto , Kouhei Nakata
发明人： Kouji Okamoto , Kouhei Nakata
IPC分类号： G09G5/00 , H03D13/00
CPC分类号： G11B20/1403 , G11B20/10009 , G11B20/10046 , G11B20/10222 , G11B20/10425 , G11B2220/2562
摘要： In a synchronous reproduction signal processor, when a phase error between reproduction data and a clock is repeatedly detected such that a clock synchronized with a reproduction signal is generated based on the phase error, a filtering process unit (34) performs a filtering process which performs a weighed addition with respect to a phase error series prior to the current time from a phase error calculation unit (33) using, e.g., a FIR filter with a plurality of taps so as to generate a reference value under reduced influence of noise mixed in the phase error series by feedback correction. A cross detection unit (32) detects the timing with which the sampled reproduction data crosses the reference value generated by the filtering process unit (34). This allows effective use of the dynamic range of the feedbacked reference value without limiting it, and simultaneously achieves the enhancement of noise immunity.
摘要翻译：在同步再现信号处理器中，当重复检测再现数据和时钟之间的相位误差，从而基于相位误差产生与再现信号同步的时钟时，滤波处理单元（34）执行滤波处理相对于来自相位误差计算单元（33）的当前时间之前的相位误差系列的加权加法，其使用例如具有多个抽头的FIR滤波器，以便在减少的混合噪声的影响下产生参考值相位误差系列通过反馈校正。交叉检测单元（32）检测采样再现数据与由滤波处理单元（34）生成的参考值相交的定时。这允许有效地使用反馈参考值的动态范围而不限制它，并且同时实现抗噪声的增强。

12. 发明申请

US20090223532A1 PERMANENT WAVE TREATMENT METHOD AND DEVICE 审中-公开
标题翻译：永久性波浪处理方法和装置
公开(公告)号：US20090223532A1
公开(公告)日：2009-09-10
申请号：US11719453
申请日：2006-02-02
申请人： Tomoaki Takada , Kenji Miyamoto , Kazuya Yamanaka , Terumi Shibano , Kouji Okamoto , Ryoji Kitamura
发明人： Tomoaki Takada , Kenji Miyamoto , Kazuya Yamanaka , Terumi Shibano , Kouji Okamoto , Ryoji Kitamura
IPC分类号： A45D7/02 , A45D2/12 , A45D20/18
CPC分类号： A45D20/44 , A45D2/24 , A45D4/18 , A45D7/02 , A45D20/46
摘要： A permanent wave treatment device has a heating means (3) for setting hair of a to-be-treated person in a heated environment, a rod (R) on which the hair is wound and that is formed so that air can flow through it, a suction means (4) for making the pressure inside the rod negative, and a connection means (7) for connecting the rod and the suction means.
摘要翻译：永久性波浪处理装置具有加热装置（3），用于在被加热的环境中设置待处理的人的毛发，其上缠绕有毛发的杆（R），并且形成为使得空气能够流过它，用于使杆内的压力为负的抽吸装置（4）和用于连接杆和抽吸装置的连接装置（7）。

13. 发明申请

US20090086588A1 Timing extractor, and information playback apparatus and dvd device using the timing extractor 有权
标题翻译：定时提取器，以及使用定时提取器的信息播放装置和DVD设备
公开(公告)号：US20090086588A1
公开(公告)日：2009-04-02
申请号：US11667299
申请日：2006-07-18
申请人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri
发明人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri
IPC分类号： G11B21/08
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10222 , G11B20/1403 , G11B2020/1476 , G11B2220/2562 , H03L7/091 , H03L7/1976 , H04L7/02 , H04L7/033
摘要： In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation section 2 calculates the ratio between the frequency of the playback signal and the frequency of the output clock of a frequency synthesizer 6 by utilizing a specific pattern and a specific pattern appearing interval in the playback signal. A control section 4 controls the frequency dividing rate of the frequency synthesizer 6 in such a manner that the frequency ratio calculated by the frequency ratio calculation section 2 has a set value. Thus, as compared with a case in which the output clock of the frequency synthesizer 6 is a high-frequency fixed-rate clock, it is not necessary to operate the digital circuits at high speeds. Consequently, even in cases where the playback frequency (the playback rate) of the signal changes with time, the decimation rate at which pulses of a fixed clock are eliminated is constant, thereby reducing power consumption.
摘要翻译：在从再现信号中提取定时信息的前馈定时提取器中，频率比计算部分2通过利用特定的模式和特定的模式来计算重放信号的频率与频率合成器6的输出时钟的频率之间的比率重放信号中的图案出现间隔。控制部分4以频率比计算部分2计算出的频率比具有设定值的方式控制频率合成器6的分频率。因此，与频率合成器6的输出时钟为高频固定速度时钟的情况相比，不需要以高速操作数字电路。因此，即使在信号的重放频率（播放速度）随时间变化的情况下，消除固定时钟的脉冲的抽取率恒定，从而降低功耗。

14. 发明授权

US07423948B2 Phase error detecting circuit and synchronization clock extraction circuit 失效
标题翻译：相位误差检测电路和同步时钟提取电路
公开(公告)号：US07423948B2
公开(公告)日：2008-09-09
申请号：US10533434
申请日：2004-06-11
申请人： Akira Kawabe , Kouji Okamoto
发明人： Akira Kawabe , Kouji Okamoto
IPC分类号： G11B7/00
CPC分类号： H03L7/091 , G11B20/10009 , G11B20/18 , H04L7/0334
摘要： In a phase error detecting circuit used in a synchronous clock extracting circuit for extracting a clock which is synchronized with reproduced data, a cross reference value generator 72 inputs, as a rising cross reference value S5, rising phase error data S3 calculated in a phase error calculator 71 to a rising cross detector 70a and inputs, as a falling cross reference value S6, falling phase error data S4 similarly calculated to a falling cross detector 70b. Each of the cross detectors 70a and 70b calculates a difference value between the value of the reproduced data at a sampling point and the inputted cross reference value (cross offset value) S5 or S6 and outputs a rising or falling cross detection signal when one of two difference values at consecutive sampling points is negative and the other thereof is positive. Accordingly, a capture range is enlarged.
摘要翻译：在用于提取与再现数据同步的时钟的同步时钟提取电路中使用的相位误差检测电路中，交叉参考值发生器72输入作为上升交叉参考值S 5的上升相位误差数据S 3，将相位误差计算器71提供给上升交叉检测器70a，并将与下降交叉检测器70b类似地计算出的下降相位误差数据S 4输入作为下降交叉参考值S6。交叉检测器70a和70b中的每一个计算采样点的再现数据的值与输入的交叉参考值（交叉偏移值）S 5或S 6之间的差值，并输出上升或下降交叉检测信号当连续采样点的两个差值之一为负，另一个为正时。因此，捕获范围被扩大。

15. 发明申请

US20050018578A1 Playback signal processing apparatus and optical disc device 失效
标题翻译：播放信号处理装置和光盘装置
公开(公告)号：US20050018578A1
公开(公告)日：2005-01-27
申请号：US10871062
申请日：2004-06-21
申请人： Youichi Ogura , Toshihiko Takahashi , Kazutoshi Aida , Kouji Okamoto
发明人： Youichi Ogura , Toshihiko Takahashi , Kazutoshi Aida , Kouji Okamoto
IPC分类号： G11B3/00 , G11B5/09 , G11B20/10 , G11B20/14 , G11B20/22
CPC分类号： G11B20/10425 , G11B20/10009 , G11B20/10037 , G11B20/10055 , G11B20/10222 , G11B20/1403 , G11B20/22 , G11B2020/1288 , G11B2220/2541
摘要： When generating a sampling clock of an A/D converter for digitizing a playback signal from an optical disc, an over sampling clock generated by a PLL is used. Further, zerocross position information and reference information of a playback digital signal that is obtained by A/D conversion using the over sampling clock are converted into those synchronized with the channel bit clock by an operation cycle conversion unit, and then supplied to a PRML signal processing unit and a level judgement binarization unit.
摘要翻译：当产生用于数字化来自光盘的重放信号的A / D转换器的采样时钟时，使用由PLL产生的过采样时钟。此外，通过使用过采样时钟的A / D转换获得的重放数字信号的零交叉位置信息和参考信息被转换为与通道位时钟同步的操作周期转换单元，然后被提供给PRML信号处理单元和级别判断二值化单元。

16. 发明授权

US06608524B2 Automatic gain control circuit 失效
公开(公告)号：US06608524B2
公开(公告)日：2003-08-19
申请号：US10163456
申请日：2002-06-07
申请人： Akira Kawabe , Kouji Okamoto
发明人： Akira Kawabe , Kouji Okamoto
IPC分类号： H03G320
CPC分类号： H03G3/3084
摘要： In a state where a PLL circuit is not locked, a gain control signal according to the difference between a peak value of a reproduced signal and the upper or lower limit value of the dynamic range of an A/D converter is given to a variable gain amplifier. In a state where the PLL circuit is locked, a gain control signal according to the difference between the reproduced signal and a reference value that corresponds to a level to which the reproduced signal belongs is given to the variable gain amplifier for each sampling point of the A/D converter. The variable gain amplifier amplifies the reproduced signal with a gain according to the gain control signal.

17. 发明授权

US06393084B1 Clock recovery circuit 有权
公开(公告)号：US06393084B1
公开(公告)日：2002-05-21
申请号：US09734183
申请日：2000-12-12
申请人： Kouji Okamoto
发明人： Kouji Okamoto
IPC分类号： H03D324
摘要： An oscillating clock frequency of a VFO (variable frequency oscillator) is controlled, using the results of addition of an output from a constant multiplier and an output from an accumulator, which is a result of accumulation of outputs from another constant multiplier, based on a phase error signal by setting the output from an enable-provided latch to 0 during a frequency pull-in operation. A control signal generating portion outputs a pulse at the Hi level as a control signal when completion of frequency pull-in is detected. The latch stores the output from the constant multiplier at the time when the control signal is supplied. Thus, a phase pull-in operation is started in the state where a latch output representing a frequency correction component is obtained. During the phase pull-in operation, the VFO is controlled using the result of addition of an output from the multiplier, an output from the accumulator and an output from the latch. Thus, high speed phase pull-in can be achieved, for example, in reproducing data signal recorded in a recording medium.

18. 发明申请

US20120081339A1 DIGITAL PLL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND DISPLAY APPARATUS 有权
标题翻译：数字PLL电路，半导体集成电路和显示设备
公开(公告)号：US20120081339A1
公开(公告)日：2012-04-05
申请号：US13313638
申请日：2011-12-07
申请人： Hiroki MOURI , Kouji Okamoto , Fumiaki Senoue
发明人： Hiroki MOURI , Kouji Okamoto , Fumiaki Senoue
IPC分类号： G09G5/00 , H03L7/08
CPC分类号： H03D13/003 , H03L7/087 , H03L2207/50
摘要： In a digital PLL circuit, a phase comparison circuit counts the numbers of transitions of a reference clock and an oscillation clock, sets a time taken until the number of transitions of the reference clock reaches a reference count value as a phase comparison time period, and detects, as a phase error value, a difference between a target count value, obtained based on a magnification value of a desired oscillating frequency with respect to the frequency of the reference clock and the reference count value, and the number of transitions of the oscillation clock in the phase comparison time period. A smoothing circuit smoothes the phase error value. A digitally-controlled oscillation circuit controls the frequency of the oscillation clock in accordance with the phase error value smoothed by the smoothing circuit.
摘要翻译：在数字PLL电路中，相位比较电路对参考时钟和振荡时钟的转换次数进行计数，将所参考时钟的转换次数达到参考计数值所花费的时间设置为相位比较时间段，以及将作为相位误差值的目标计数值相对于基准时钟的频率和基准计数值的期望的振荡频率的倍率值与振荡的转移次数进行比较，时钟在相位比较时间段。平滑电路平滑相位误差值。数字控制振荡电路根据平滑电路平滑的相位误差值来控制振荡时钟的频率。

19. 发明申请

US20110206144A1 RECEIVER AND TRANSMISSION/RECEPTION SYSTEM 审中-公开
标题翻译：接收器和传输/接收系统
公开(公告)号：US20110206144A1
公开(公告)日：2011-08-25
申请号：US13101679
申请日：2011-05-05
申请人： Akira YAMAMOTO , Kouji Okamoto , Yoshinori Shirakawa
发明人： Akira YAMAMOTO , Kouji Okamoto , Yoshinori Shirakawa
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： H04L27/206 , H04L1/0057 , H04L1/206 , H04L27/2332
摘要： In a wireless receiver, a “variance” of an intermediate output signal of a demodulation section is calculated by a variance calculation section, and the calculated variance is used as a signal quality indicator which indicates the degree of goodness of a receiving condition. For example, when the “variance” is small, a gain of a low-noise amplifier is reduced, or an operation clock frequency of a baseband oscillator is reduced, etc. Thus, when the receiving condition indicated by the indicator is good and sufficient performance is ensured, the performance can be slightly lowered to reduce power consumption. The “variance” is a compact indicator which can be calculated using a simple operation, and is used as a new signal quality indicator.
摘要翻译：在无线接收机中，通过方差计算部分计算出解调部分的中间输出信号的“方差”，将所计算出的方差作为表示接收条件良好程度的信号质量指标。例如，当“方差”小时，降低了低噪声放大器的增益，或降低了基带振荡器的操作时钟频率等。因此，当指示符指示的接收条件良好且足够时性能得到保证，性能可以稍微降低以降低功耗。 “方差”是可以使用简单操作计算的紧凑指示器，并且用作新的信号质量指示符。

20. 发明申请

US20110205444A1 RECEIVER, SIGNAL PROCESSING APPARATUS, AND VIDEO DISPLAY APPARATUS 有权
标题翻译：接收器，信号处理装置和视频显示装置
公开(公告)号：US20110205444A1
公开(公告)日：2011-08-25
申请号：US13101654
申请日：2011-05-05
申请人： Akira Yamamoto , Kouji Okamoto , Yoshinori Shirakawa
发明人： Akira Yamamoto , Kouji Okamoto , Yoshinori Shirakawa
IPC分类号： H04N5/455
CPC分类号： H04N7/163 , G09G5/006 , G09G2330/021 , G09G2340/12 , G09G2370/12 , G09G2370/16 , G09G2370/20 , G09G2370/22 , H04N21/4305 , H04N21/43615 , H04N21/44
摘要： A receiver for receiving signals in a plurality of transmission schemes, reducing the circuit size thereof successfully. The receiver for receiving a baseband signal and a modulated signal, includes a first PLL circuit configured to generate a first internal clock based on an external clock synchronized with the baseband signal; a demodulator configured to demodulate the modulated signal to output the demodulated signal; a selector configured to select one of the baseband signal or the demodulated signal; and a first CDR circuit configured to generate a recovered clock and recovered data from the signal selected by the selector, by using the first internal clock.
摘要翻译：一种用于以多个传输方案接收信号的接收机，其成功地减小了其电路尺寸。用于接收基带信号和调制信号的接收机包括：第一PLL电路，被配置为基于与基带信号同步的外部时钟产生第一内部时钟; 解调器，被配置为解调所述调制信号以输出所述解调信号; 选择器，被配置为选择所述基带信号或所述解调信号之一; 以及第一CDR电路，被配置为通过使用第一内部时钟从由选择器选择的信号中产生恢复的时钟和恢复的数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式