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11. 发明授权

US08883598B2 Thin capped channel layers of semiconductor devices and methods of forming the same 有权
标题翻译：半导体器件的薄封装沟道层及其形成方法
公开(公告)号：US08883598B2
公开(公告)日：2014-11-11
申请号：US13412099
申请日：2012-03-05
申请人： Che-Ting Chu , Shih-Hsun Chang , Pang-Yen Tsai
发明人： Che-Ting Chu , Shih-Hsun Chang , Pang-Yen Tsai
IPC分类号： H01L21/8232 , H01L21/20 , H01L29/66 , H01L29/10
CPC分类号： H01L29/1054 , H01L29/66651
摘要： Semiconductor devices and methods of forming the same. The method includes providing a semiconductor substrate having a channel layer over the substrate. A capping layer including silicon and having a first thickness is formed over the channel layer. The capping layer is partially oxidized to form an oxidized portion of the capping layer. The oxidized portion of the capping layer is removed to form a thinned capping layer having a second thickness less than the first thickness.
摘要翻译：半导体器件及其形成方法。该方法包括提供在衬底上方具有沟道层的半导体衬底。包含硅并具有第一厚度的覆盖层形成在沟道层上。覆盖层被部分氧化以形成覆盖层的氧化部分。去除覆盖层的氧化部分以形成具有小于第一厚度的第二厚度的变薄的覆盖层。

12. 发明授权

US08629426B2 Source/drain stressor having enhanced carrier mobility manufacturing same 有权
标题翻译：具有增强的载流子迁移率制造的源极/漏极应力源相同
公开(公告)号：US08629426B2
公开(公告)日：2014-01-14
申请号：US12960237
申请日：2010-12-03
申请人： Chin-Hsiang Lin , Jeff J. Xu , Pang-Yen Tsai
发明人： Chin-Hsiang Lin , Jeff J. Xu , Pang-Yen Tsai
IPC分类号： H01L21/00
CPC分类号： H01L29/66575 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/66628 , H01L29/66636 , H01L29/7848 , H01L29/7849
摘要： Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer.
摘要翻译：公开了可以增强载流子迁移率的各种源极/漏极应力源及其制造方法。示例性源极/漏极应力器包括设置在第二材料的衬底上的第一材料的种子层，第一材料不同于第二材料; 设置在种子层上的松弛外延层; 以及设置在松弛外延层上的外延层。

13. 发明授权

US08481402B2 Epitaxy silicon on insulator (ESOI) 有权
标题翻译：外延绝缘体硅（ESOI）
公开(公告)号：US08481402B2
公开(公告)日：2013-07-09
申请号：US13285796
申请日：2011-10-31
申请人： Ming-Hua Yu , Tze-Liang Lee , Pang-Yen Tsai
发明人： Ming-Hua Yu , Tze-Liang Lee , Pang-Yen Tsai
IPC分类号： H01L21/76 , H01L21/20
CPC分类号： H01L29/0649 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/517 , H01L29/6659 , H01L29/7843 , H01L29/7846
摘要： Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.
摘要翻译：提供了SOI衬底中具有STI区域的半导体器件的方法和结构。半导体结构包括在衬底上形成的SOI外延岛。该结构还包括围绕SOI岛的STI结构。 STI结构包括在衬底上的第二外延层和在第二外延层上的第二电介质层。一种半导体制造方法包括在衬底上形成介电层并围绕延伸穿过介电层的隔离沟槽围绕衬底中的器件制造区域。该方法还包括用第一外延层填充隔离沟槽，并在器件制造区域上方和第一外延层上形成第二外延层。然后用绝缘电介质代替第一外延层的一部分，然后在器件制造区域内形成诸如晶体管的器件的第二外延层。

14. 发明申请

US20120043641A1 Epitaxy Silicon on Insulator (ESOI) 有权
标题翻译：绝缘体上的外延硅（ESOI）
公开(公告)号：US20120043641A1
公开(公告)日：2012-02-23
申请号：US13285796
申请日：2011-10-31
申请人： Ming-Hua Yu , Tze-Liang Lee , Pang-Yen Tsai
发明人： Ming-Hua Yu , Tze-Liang Lee , Pang-Yen Tsai
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/517 , H01L29/6659 , H01L29/7843 , H01L29/7846
摘要： Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.
摘要翻译：提供了SOI衬底中具有STI区域的半导体器件的方法和结构。半导体结构包括在衬底上形成的SOI外延岛。该结构还包括围绕SOI岛的STI结构。 STI结构包括在衬底上的第二外延层和在第二外延层上的第二电介质层。一种半导体制造方法包括在衬底上形成介电层并围绕延伸穿过介电层的隔离沟槽围绕衬底中的器件制造区域。该方法还包括用第一外延层填充隔离沟槽，并在器件制造区域上方和第一外延层上形成第二外延层。然后用绝缘电介质代替第一外延层的一部分，然后在器件制造区域内形成诸如晶体管的器件的第二外延层。

15. 发明申请

US20110008951A1 Method of manufacturing strained-silicon semiconductor device 有权
标题翻译：制造应变硅半导体器件的方法
公开(公告)号：US20110008951A1
公开(公告)日：2011-01-13
申请号：US12870365
申请日：2010-08-27
申请人： Yun-Hsiu Chen , Syun-Ming Jang , Pang-Yen Tsai
发明人： Yun-Hsiu Chen , Syun-Ming Jang , Pang-Yen Tsai
IPC分类号： H01L21/20
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/7848
摘要： A method for fabricating a strained-silicon semiconductor device to ameliorate undesirable variation in selectively grown epitaxial film thickness. The layout or component configuration for the proposed semiconductor device is evaluated to determine areas of relatively light or dense population in order to determine whether local-loading-effect defects are likely to occur. If a possibility of such defects occurring exists, a dummy pattern of epitaxial structures may be indicated. If so, the dummy pattern appropriate to the proposed layout is created, incorporated into the mask design, and then implemented on the substrate along with the originally-proposed component configuration.
摘要翻译：一种用于制造应变硅半导体器件以改善选择性生长的外延膜厚度的不期望的变化的方法。评估所提出的半导体器件的布局或组件配置以确定相对较轻或密集的群体的区域，以便确定是否可能发生局部加载效应的缺陷。如果存在这种缺陷的可能性，则可以指示外延结构的虚拟图案。如果是这样，则创建适合于所提出的布局的虚拟图案，并入到掩模设计中，然后与原始提出的部件配置一起在基板上实现。

16. 发明授权

US07803690B2 Epitaxy silicon on insulator (ESOI) 有权
标题翻译：外延绝缘体硅（ESOI）
公开(公告)号：US07803690B2
公开(公告)日：2010-09-28
申请号：US11521667
申请日：2006-09-15
申请人： Ming-Hua Yu , Tze-Liang Lee , Pang-Yen Tsai
发明人： Ming-Hua Yu , Tze-Liang Lee , Pang-Yen Tsai
IPC分类号： H01L21/76
CPC分类号： H01L29/0649 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/517 , H01L29/6659 , H01L29/7843 , H01L29/7846
摘要： Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.
摘要翻译：提供了SOI衬底中具有STI区域的半导体器件的方法和结构。半导体结构包括在衬底上形成的SOI外延岛。该结构还包括围绕SOI岛的STI结构。 STI结构包括在衬底上的第二外延层和在第二外延层上的第二电介质层。一种半导体制造方法包括在衬底上形成介电层并围绕延伸穿过介电层的隔离沟槽围绕衬底中的器件制造区域。该方法还包括用第一外延层填充隔离沟槽，并在器件制造区域上方和第一外延层上形成第二外延层。然后用绝缘电介质代替第一外延层的一部分，然后在器件制造区域内形成诸如晶体管的器件的第二外延层。

17. 发明授权

US07732289B2 Method of forming a MOS device with an additional layer 有权
标题翻译：用附加层形成MOS器件的方法
公开(公告)号：US07732289B2
公开(公告)日：2010-06-08
申请号：US11174683
申请日：2005-07-05
申请人： Chii-Ming Wu , Chih-Wei Chang , Pang-Yen Tsai , Chih-Chien Chang
发明人： Chii-Ming Wu , Chih-Wei Chang , Pang-Yen Tsai , Chih-Chien Chang
IPC分类号： H01L21/366
CPC分类号： H01L29/665 , H01L21/28114 , H01L29/42376 , H01L29/6659 , H01L29/66636 , H01L29/7843
摘要： A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.
摘要翻译：提供了一种形成MOS器件的方法。该方法包括提供半导体衬底，在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在半导体衬底中形成源/漏区，在源上形成附加层，优选通过外延生长 /漏极区域，并且至少将附加层的顶部部分硅化。附加层补偿在制造过程中损失的半导体材料的至少一部分，并且增加源极/漏极硅化物和衬底之间的距离。结果，泄漏电流降低。使用优选实施例形成的晶体管优选地包括在栅极上的硅化物，其中硅化物延伸超过栅电极的侧壁边界。

18. 发明授权

US07615426B2 PMOS transistor with discontinuous CESL and method of fabrication 有权
标题翻译：具有不连续CESL的PMOS晶体管及其制造方法
公开(公告)号：US07615426B2
公开(公告)日：2009-11-10
申请号：US11118730
申请日：2005-04-29
申请人： Chih-Hao Wang , Yen-Ping Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Yen-Ping Wang , Pang-Yen Tsai
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/76 , H01L29/94 , H01L27/01
CPC分类号： H01L29/165 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7843 , H01L29/7848 , H01L29/7849
摘要： A transistor having a discontinuous contact etch stop layer comprising: a substrate having a surface, a gate dielectric on said surface of said substrate, a gate electrode on said gate dielectric, a spacer along a sidewall of said gate dielectric and gate electrode, a source and a drain formed on opposite sides, respectively, of said gate dielectric and said gate electrode, the source and drain defining a channel region having a channel length extending substantially from said source to said drain, in the substrate therebetween, and a contact etch stop layer on said gate and said spacers, and said source and drain. The contact etch stop layer is substantially locally continuous in a direction perpendicular to the channel region length and substantially locally discontinuous in a direction parallel to the channel region length.
摘要翻译：一种具有不连续接触蚀刻停止层的晶体管，包括：具有表面的衬底，所述衬底的所述表面上的栅极电介质，所述栅极电介质上的栅极电极，沿着所述栅极电介质和栅电极的侧壁的间隔物，源极以及分别在所述栅极电介质和所述栅电极的相对侧上形成的漏极，所述源极和漏极限定了沟道区，所述沟道区具有基本上从所述源延伸到所述漏极的沟道长度，以及在其间的衬底中的接触蚀刻停止所述栅极和所述间隔物上的层，以及所述源极和漏极。接触蚀刻停止层在垂直于沟道区长度的方向上基本上局部连续，并且在平行于沟道区长度的方向上基本上局部不连续。

19. 发明申请

US20090090935A1 High Performance CMOS Device Design 有权
标题翻译：高性能CMOS器件设计
公开(公告)号：US20090090935A1
公开(公告)日：2009-04-09
申请号：US12330961
申请日：2008-12-09
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L29/78
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.
摘要翻译：半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。缓冲层优选具有比下面的半导体衬底更大的晶格常数。半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

20. 发明授权

US5396666A Flush device for toilet 失效
标题翻译：马桶冲洗装置
公开(公告)号：US5396666A
公开(公告)日：1995-03-14
申请号：US167250
申请日：1993-12-16
申请人： Pang-Yen Tsai , Chien-Liang Hsiao
发明人： Pang-Yen Tsai , Chien-Liang Hsiao
IPC分类号： E03D1/14 , E03D1/30
CPC分类号： E03D1/308 , E03D1/142
摘要： A flush device for toilet comprises within a water tank a support arm, a restricting member and a outlet valve thereof attached in series to an overflow tube, and an actuating assembly including a actuator arm thereof connected with the outlet valve via the support arm by a lift wire or chain thereinbetween. This disclosure has been characterized in a pulley on the top of the support arm, a displaceable and inversible restricting member and a flexible actuating assembly which facilitate a varying the discharge amount of the flush water and a smooth operation in different moods.
摘要翻译：一种用于马桶的冲洗装置，包括在水箱内的一个支撑臂，一个限制构件和一个与溢流管串联连接的出口阀，以及一个致动组件，包括一个致动器臂，它通过支撑臂与出口阀连接，电线或链条之间。本公开的特征在于支撑臂的顶部上的滑轮，可移动和可逆的限制构件和柔性致动组件，其有助于改变冲洗水的排出量和在不同情绪下的平稳操作。

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