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11. 发明授权

US08110483B2 Forming an extremely thin semiconductor-on-insulator (ETSOI) layer 有权
标题翻译：形成极薄的绝缘体上半导体（ETSOI）层
公开(公告)号：US08110483B2
公开(公告)日：2012-02-07
申请号：US12603737
申请日：2009-10-22
申请人： Wagdi W. Abadeer , Lilian Kamal, legal representative , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：公开了用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

12. 发明授权

US07776680B2 Complementary metal oxide semiconductor device with an electroplated metal replacement gate 失效
标题翻译：具有电镀金属置换栅的互补金属氧化物半导体器件
公开(公告)号：US07776680B2
公开(公告)日：2010-08-17
申请号：US11968885
申请日：2008-01-03
申请人： Veeraraghavan S. Basker , John M. Cotte , Hariklia Deligianni , Toshiharu Furukawa , Vamsi K. Paruchuri , William R. Tonti
发明人： Veeraraghavan S. Basker , John M. Cotte , Hariklia Deligianni , Toshiharu Furukawa , Vamsi K. Paruchuri , William R. Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L29/517 , H01L29/66545
摘要： Disclosed herein are embodiments of a method of forming a complementary metal oxide semiconductor (CMOS) device that has at least one high aspect ratio gate structure with a void-free and seam-free metal gate conductor layer positioned on top of a relatively thin high-k gate dielectric layer. These method embodiments incorporate a gate replacement strategy that uses an electroplating process to fill, from the bottom upward, a high-aspect ratio gate stack opening with a metal gate conductor layer. The source of electrons for the electroplating process is a current passed directly through the back side of the substrate. This eliminates the need for a seed layer and ensures that the metal gate conductor layer will be formed without voids or seams. Furthermore, depending upon the embodiment, the electroplating process is performed under illumination to enhance electron flow to a given area (i.e., to enhance plating) or in darkness to prevent electron flow to a given area (i.e., to prevent plating).
摘要翻译：本文公开了一种形成互补金属氧化物半导体（CMOS）器件的方法的实施例，该器件具有至少一个高纵横比栅极结构，其中无空隙和无缝的金属栅极导体层位于相对薄的高压 k栅介质层。这些方法实施例包括栅极替换策略，其使用电镀工艺从底部向上填充具有金属栅极导体层的高纵横比栅极堆叠开口。用于电镀工艺的电子源是直接通过衬底背面的电流。这消除了对种子层的需要，并且确保金属栅极导体层将形成为没有空隙或接缝。此外，根据实施例，电镀工艺在照明下进行，以增强电子流向给定区域（即，为了增强电镀）或在黑暗中以防止电子流向给定区域（即防止电镀）。

13. 发明授权

US06555891B1 SOI hybrid structure with selective epitaxial growth of silicon 有权
公开(公告)号：US06555891B1
公开(公告)日：2003-04-29
申请号：US09690674
申请日：2000-10-17
申请人： Toshiharu Furukawa , Jack A. Mandelman , Dan Moy , Byeongju Park , William R. Tonti
发明人： Toshiharu Furukawa , Jack A. Mandelman , Dan Moy , Byeongju Park , William R. Tonti
IPC分类号： H01L2900
CPC分类号： H01L27/10894 , H01L21/76262 , H01L21/76264 , H01L21/76278 , H01L21/84 , H01L27/10861 , H01L27/1207
摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

14. 发明授权

US06380027B2 Dual tox trench dram structures and process using V-groove 失效
标题翻译：双毒tox沟结构和工艺采用V型槽
公开(公告)号：US06380027B2
公开(公告)日：2002-04-30
申请号：US09225127
申请日：1999-01-04
申请人： Toshiharu Furukawa , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl J. Radens , William R. Tonti , Mary E. Weybright
发明人： Toshiharu Furukawa , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl J. Radens , William R. Tonti , Mary E. Weybright
IPC分类号： H01L21242
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829 , H01L27/10894
摘要： A structure and method for simultaneously forming array structures and support structures on a substrate comprises forming the array structures to have a V-groove, forming the support structures to have a planar surface, and simultaneously forming a first oxide in the V-groove and a second oxide in the planar surface, wherein the first oxide is thicker than the second oxide.
摘要翻译：用于在衬底上同时形成阵列结构和支撑结构的结构和方法包括：形成阵列结构以具有V形槽，形成支撑结构以具有平坦表面，同时在V形槽中形成第一氧化物，以及其中所述第一氧化物比所述第二氧化物厚。

15. 发明申请

US20090206447A1 ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD 有权
标题翻译：抗保护器件结构和电镀电路结构与方法
公开(公告)号：US20090206447A1
公开(公告)日：2009-08-20
申请号：US12031761
申请日：2008-02-15
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5252 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
摘要翻译：公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。在电沉积期间，可以选择性地控制通过电流路径的电流。此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。

16. 发明授权

US07381610B2 Semiconductor transistors with contact holes close to gates 有权
标题翻译：具有靠近门的接触孔的半导体晶体管
公开(公告)号：US07381610B2
公开(公告)日：2008-06-03
申请号：US11163966
申请日：2005-11-04
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , William R. Tonti
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , William R. Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28061 , H01L21/28114
摘要： A structure and a method for forming the same. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.
摘要翻译：一种结构及其形成方法。该结构包括（a）包括设置在第一和第二S / D区之间的沟道区的半导体层; （b）沟道区上的栅介质区; （c）栅极电介质区域上的栅极区域，并且通过栅极电介质区域与沟道区域电绝缘; （d）栅极区域上的保护伞区域，其中保护伞区域包括第一介电材料，并且其中栅极区域完全处于保护伞区域的阴影中; 和（e）直接在第二S / D区域上方并电连接到第二S / D区域的填充接触孔（i）和（ii）与保护伞区域的边缘对准，其中接触孔通过一个层间介电层（ILD）层，其包括不同于第一介电材料的第二电介质材料。

17. 发明申请

US20120098087A1 FORMING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER 审中-公开
标题翻译：形成极薄的半导体绝缘体（ETSOI）层
公开(公告)号：US20120098087A1
公开(公告)日：2012-04-26
申请号：US13342423
申请日：2012-01-03
申请人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L27/12 , H01L21/306 , H01L21/3065 , H01L21/265
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

18. 发明授权

US08043966B2 Method for monitoring patterning integrity of etched openings and forming conductive structures with the openings 有权
标题翻译：用于监测蚀刻开口的图案完整性并与开口形成导电结构的方法
公开(公告)号：US08043966B2
公开(公告)日：2011-10-25
申请号：US12101329
申请日：2008-04-11
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
IPC分类号： H01L21/44
CPC分类号： H01L21/76879 , C25D5/10 , C25D5/12 , C25D7/123 , C25D21/12 , H01L21/2885 , H01L21/76802 , H01L22/14 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a method that both monitors patterning integrity of etched openings (i.e., ensures that lithographically patterned and etched openings are complete) and forms on-chip conductive structures (e.g., contacts, interconnects, fuses, anti-fuses, capacitors, etc.) within such openings. The method embodiments incorporate an electro-deposition process to provide both the means by which pattern integrity of etched openings can be monitored and also the metallization required for the formation of conductive structures within the openings. Specifically, during the electro-deposition process, electron flow is established by applying a current to the back side of the semiconductor wafer, thus, eliminating the need for a seed layer. Electron flow through the wafer and into the electroplating solution is then monitored and used as an indicator of electroplating in the etched openings and, thereby, as an indicator that the openings are completely etched.
摘要翻译：公开了一种方法的实施例，两者都监控图案化蚀刻开口的完整性（即，确保光刻图案和蚀刻的开口完整），并且形成片上导电结构（例如，触点，互连，熔断器，抗熔丝，电容器等）。）在这样的开口内。该方法实施例包括电沉积工艺，以提供能够监测蚀刻开口的图案完整性的装置以及在开口内形成导电结构所需的金属化。具体地，在电沉积过程中，通过向半导体晶片的背面施加电流来建立电子流动，从而消除了种子层的需要。然后监测通过晶片并进入电镀溶液的电子流，并将其用作蚀刻开口中的电镀的指示剂，从而作为开口被完全蚀刻的指示器。

19. 发明申请

US20110169129A1 ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD 有权
标题翻译：抗保护器件结构和电镀电路结构与方法
公开(公告)号：US20110169129A1
公开(公告)日：2011-07-14
申请号：US13072023
申请日：2011-03-25
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
IPC分类号： H01L23/525
CPC分类号： H01L23/5252 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
摘要翻译：公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。在电沉积期间，可以选择性地控制通过电流路径的电流。此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。

20. 发明授权

US07935621B2 Anti-fuse device structure and electroplating circuit structure and method 有权
标题翻译：反熔丝器件结构及电镀电路结构及方法
公开(公告)号：US07935621B2
公开(公告)日：2011-05-03
申请号：US12031761
申请日：2008-02-15
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
IPC分类号： H01L21/44
CPC分类号： H01L23/5252 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
摘要翻译：公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。在电沉积期间，可以选择性地控制通过电流路径的电流。此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。

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