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11. 发明申请

US20060171477A1 Digital transmission circuit and method providing selectable power consumption via single-ended or differential operation 有权
公开(公告)号：US20060171477A1
公开(公告)日：2006-08-03
申请号：US11050605
申请日：2005-02-03
申请人： Juan-Antonio Carballo , Kevin Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Kevin Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H04L25/00
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via single-ended or differential operation improves the flexibility of an interface while reducing power consumption when possible. A differential path is provided through the transmitter output driver stages and portions are selectively disabled when the transmission circuit is in a lower-power operating mode. A single-ended to differential converter circuit can be used to construct a differential signal for output to the final driver stage. The selection of power mode can be made via feedback from a channel quality measurement unit or may be hardwired or selected under programmatic control. The longer delay or skew of the lower-power single-ended mode is compensated for by the relaxed requirements of the channel when conditions permit the use of the lower-power single-ended mode.

12. 发明申请

US20060172715A1 Digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices 有权
标题翻译：数字传输电路和方法通过多个加权驱动器片提供可选择的功耗
公开(公告)号：US20060172715A1
公开(公告)日：2006-08-03
申请号：US11050019
申请日：2005-02-03
申请人： Juan-Antonio Carballo , Kevin Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Kevin Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H04B1/04 , H01Q11/12 , H03F3/68
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译：通过多个加权驱动器片提供可选择的功耗的数字传输电路和方法提高了接口的灵活性，同时在可能的同时降低了发射机功耗，面积和复杂度。级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。

13. 发明授权

US06724221B2 Circuitry having exclusive-OR and latch function, and method therefor 失效
标题翻译：具有异或和锁存功能的电路及其方法
公开(公告)号：US06724221B2
公开(公告)日：2004-04-20
申请号：US10112513
申请日：2002-03-28
申请人： Juan-Antonio Carballo , David William Boerstler , Jeffrey L. Burns , Kevin John Nowka , Li Shi
发明人： Juan-Antonio Carballo , David William Boerstler , Jeffrey L. Burns , Kevin John Nowka , Li Shi
IPC分类号： H03K1921
CPC分类号： H03K19/215
摘要： In one form of the invention, circuitry having exclusive-OR and latch functionality includes timing circuitry and logic circuitry. The circuitry includes a memory, with first and second memory nodes, for storing a state and its complement, and first and second timing circuitry portions, each operable to receive at least one timing signal, coupled to the respective memory nodes. The logic circuitry includes first and second logic circuitry portions, each of which is operable to receive at least first and second data signals. Each of the logic circuitry portions is coupled in series with a conditionally conductive path of one of the respective first and second timing circuitry portions.
摘要翻译：在本发明的一种形式中，具有异或和锁存功能的电路包括定时电路和逻辑电路。电路包括具有用于存储状态及其补码的第一和第二存储器节点的存储器，以及第一和第二定时电路部分，每个定时电路部分可操作以接收耦合到相应存储器节点的至少一个定时信号。逻辑电路包括第一和第二逻辑电路部分，每个逻辑电路部分可操作以接收至少第一和第二数据信号。每个逻辑电路部分与相应的第一和第二定时电路部分之一的条件导电路径串联耦合。

14. 发明授权

US06621358B2 Differential voltage controlled oscillator, and method therefor 失效
标题翻译：差分压控振荡器及其方法
公开(公告)号：US06621358B2
公开(公告)日：2003-09-16
申请号：US10015384
申请日：2001-12-17
申请人： Juan-Antonio Carballo , David William Boerstler , Jeffrey L. Burns , Ivan Vo
发明人： Juan-Antonio Carballo , David William Boerstler , Jeffrey L. Burns , Ivan Vo
IPC分类号： H03B500
CPC分类号： H03K5/133 , H03K3/0322 , H03K2005/00208 , H03K2005/00234
摘要： In a first form, a voltage controlled oscillator includes delay cells connected in a ring, and control elements connected to selectively bypass respective sets of the delay cells. The delay cells are operable to receive respective differential inputs and to generate inverted outputs. The control elements are operable to receive respective differential inputs and to generate non-inverted outputs with variable delays. The control element delays are variable responsive to respective differential control voltages.
摘要翻译：在第一形式中，压控振荡器包括以环形连接的延迟单元，以及连接到选择性地旁路各组延迟单元的控制元件。延迟单元可操作以接收相应的差分输入并产生反相输出。控制元件可操作以接收相应的差分输入并产生具有可变延迟的非反相输出。响应于各个差分控制电压，控制元件延迟是可变的。

15. 发明授权

US07269397B2 Method and apparatus for measuring communications link quality 失效
标题翻译：测量通信链路质量的方法和装置
公开(公告)号：US07269397B2
公开(公告)日：2007-09-11
申请号：US11424209
申请日：2006-06-14
申请人： Juan-Antonio Carballo , Jeffrey L. Burns , Ivan Vo
发明人： Juan-Antonio Carballo , Jeffrey L. Burns , Ivan Vo
IPC分类号： H04B17/02
CPC分类号： H04B17/20
摘要： A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.
摘要翻译：用于测量通信链路质量的方法和装置提供对实现通信链路的特定误码率（BER）的难度的精确的片上估计。连接到来自时钟/数据恢复（CDR）电路的内部信号的低成本/复杂度的累加器电路提供接收信号中的高频和低频抖动的量度。低频抖动测量用于校正可能包含错误的高频抖动测量。校正的输出可用于调整链路的操作特性或以其他方式评估链路的操作裕度。可以通过从测量的高频抖动中减去一部分低频抖动测量来执行校正，或者可以使用低频抖动测量的值来选择两个或更多个校正因子，然后将其应用于高频抖动抖动测量。

16. 发明授权

US07133654B2 Method and apparatus for measuring communications link quality 失效
标题翻译：测量通信链路质量的方法和装置
公开(公告)号：US07133654B2
公开(公告)日：2006-11-07
申请号：US10636992
申请日：2003-08-07
申请人： Juan-Antonio Carballo , Jeffrey L. Burns , Ivan Vo
发明人： Juan-Antonio Carballo , Jeffrey L. Burns , Ivan Vo
IPC分类号： H04B17/02
CPC分类号： H04B17/20
摘要： A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.
摘要翻译：用于测量通信链路质量的方法和装置提供对实现通信链路的特定误码率（BER）的难度的精确的片上估计。连接到来自时钟/数据恢复（CDR）电路的内部信号的低成本/复杂度的累加器电路提供接收信号中的高频和低频抖动的量度。低频抖动测量用于校正可能包含错误的高频抖动测量。校正的输出可用于调整链路的操作特性或以其他方式评估链路的操作裕度。可以通过从测量的高频抖动中减去一部分低频抖动测量来执行校正，或者可以使用低频抖动测量的值来选择两个或更多个校正因子，然后将其应用于高频抖动抖动测量。

17. 发明申请

US20050032491A1 Method and apparatus for measuring communications link quality 失效
标题翻译：测量通信链路质量的方法和装置
公开(公告)号：US20050032491A1
公开(公告)日：2005-02-10
申请号：US10636992
申请日：2003-08-07
申请人： Juan-Antonio Carballo , Jeffrey Burns , Ivan Vo
发明人： Juan-Antonio Carballo , Jeffrey Burns , Ivan Vo
IPC分类号： H04B17/00 , H04B17/02
CPC分类号： H04B17/20
摘要： A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.
摘要翻译：用于测量通信链路质量的方法和装置提供对实现通信链路的特定误码率（BER）的难度的精确的片上估计。连接到来自时钟/数据恢复（CDR）电路的内部信号的低成本/复杂度的累加器电路提供接收信号中的高频和低频抖动的量度。低频抖动测量用于校正可能包含错误的高频抖动测量。校正的输出可用于调整链路的操作特性或以其他方式评估链路的操作裕度。可以通过从测量的高频抖动中减去一部分低频抖动测量来执行校正，或者可以使用低频抖动测量的值来选择两个或更多个校正因子，然后将其应用于高频抖动抖动测量。

18. 发明申请

US20060223478A1 METHOD AND APPARATUS FOR MEASURING COMMUNICATIONS LINK QUALITY 失效
标题翻译：用于测量通信链路质量的方法和装置
公开(公告)号：US20060223478A1
公开(公告)日：2006-10-05
申请号：US11424209
申请日：2006-06-14
申请人： Juan-Antonio Carballo , Jeffrey Burns , Ivan Vo
发明人： Juan-Antonio Carballo , Jeffrey Burns , Ivan Vo
IPC分类号： H04B1/00 , H04B1/10 , H04B15/00
CPC分类号： H04B17/20
摘要： A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.
摘要翻译：用于测量通信链路质量的方法和装置提供对实现通信链路的特定误码率（BER）的难度的精确的片上估计。连接到来自时钟/数据恢复（CDR）电路的内部信号的低成本/复杂度的累加器电路提供接收信号中的高频和低频抖动的量度。低频抖动测量用于校正可能包含错误的高频抖动测量。校正的输出可用于调整链路的操作特性或以其他方式评估链路的操作裕度。可以通过从测量的高频抖动中减去一部分低频抖动测量来执行校正，或者可以使用低频抖动测量的值来选择两个或更多个校正因子，然后将其应用于高频抖动抖动测量。

19. 发明授权

US08271055B2 Interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage 失效
标题翻译：接口收发器功率管理方法和装置，包括受控电路复杂度和电源电压
公开(公告)号：US08271055B2
公开(公告)日：2012-09-18
申请号：US10302494
申请日：2002-11-21
申请人： Juan-Antonio Carballo , Jeffrey L. Burns
发明人： Juan-Antonio Carballo , Jeffrey L. Burns
IPC分类号： H04M1/00 , H04B1/38 , H01Q11/12 , H04B1/04
CPC分类号： H04W52/04
摘要： An interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage reduces power consumption when interface conditions will support a transceiver having reduced complexity. The power supply voltage of the reduced complexity logic is then reduced if the lowered complexity will support a lower power supply voltage. The reduced complexity in combination with a reduced power supply voltage decreases power consumption to a greater degree than reducing transceiver complexity alone.The complexity of processing blocks within the receiver and/or transmitter are adjusted in conformity with one or more selection signals and an operating voltage level is selected in accordance with the requirements of the reduced complexity circuit. An interface quality measurement circuit may provide the selection signal, so that the transceiver complexity is adjusted in response to measured interface conditions or an external pin or register bit may be coupled to a select input.
摘要翻译：包括受控电路复杂度和电源电压的接口收发器功率管理方法和装置在接口条件将支持具有降低的复杂度的收发器时降低功耗。如果降低的复杂度将支持较低的电源电压，则降低的复杂度逻辑的电源电压将被降低。与降低的电源电压相结合的降低的复杂性比仅降低收发器复杂性更大程度地降低功耗。根据一个或多个选择信号调整接收器和/或发射器内的处理块的复杂度，并且根据降低的复杂度电路的要求来选择工作电压电平。接口质量测量电路可以提供选择信号，使得响应于测量的接口条件来调整收发器复杂度，或者外部引脚或寄存器位可以耦合到选择输入。

20. 发明授权

US07315595B2 Methods and arrangements for link power reduction 失效
标题翻译：链路功率降低的方法和布置
公开(公告)号：US07315595B2
公开(公告)日：2008-01-01
申请号：US10743614
申请日：2003-12-22
申请人： Juan-Antonio Carballo
发明人： Juan-Antonio Carballo
IPC分类号： H04L7/00
CPC分类号： H04L7/0079 , H03L7/0802 , H03L7/085 , H03L7/091 , H04B1/7085 , H04L7/0331
摘要： Methods, and arrangements for extension of clock and data recovery (CDR) loop latency and deactivation of CDR circuits are disclosed. In particular, embodiments address situations in which a receiver, designed to handle spread spectrum clocking, may not always or continuously encounter spread spectrum signals. As a result, power consumption by the receivers may be reduced. Embodiments identify situations in which spread spectrum clocking is unnecessary and may adapt the CDR loop to operate with less power consumption by, e.g., reducing the operating frequency of CDR circuits. For instance, some embodiments employ a flywheel circuit, incorporated into many spread spectrum CDR loops to accelerate adjustments to a sampling clock, to determine when spread spectrum signals are not being encountered. A loop latency controller may then, advantageously, reduce power consumption by reducing frequencies of operation and voltages, and merging or simplifying stages.
摘要翻译：公开了用于延长时钟和数据恢复（CDR）环路延迟和CDR电路的去激活的方法和装置。特别地，实施例解决了设计用于处理扩频时钟的接收机可能不总是或连续地遇到扩频信号的情况。结果，可以减少接收机的功率消耗。实施例识别出不需要扩频时钟的情况，并且可以通过例如降低CDR电路的工作频率来适应CDR环路以更少的功率消耗来操作。例如，一些实施例采用飞轮电路，并入许多扩频CDR环路中以加速对采样时钟的调整，以确定何时不会遇到扩频信号。然后，有利地，循环等待时间控制器通过减少操作频率和电压，以及合并或简化阶段来降低功耗。

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