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11. 发明授权

US08589769B2 System, method and storage medium for providing fault detection and correction in a memory subsystem 有权
公开(公告)号：US08589769B2
公开(公告)日：2013-11-19
申请号：US11851496
申请日：2007-09-07
申请人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule
发明人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G11C5/04
摘要： A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.

12. 发明授权

US08296541B2 Memory subsystem with positional read data latency 失效
标题翻译：具有位置读数据延迟的内存子系统
公开(公告)号：US08296541B2
公开(公告)日：2012-10-23
申请号：US12369037
申请日：2009-02-11
申请人： Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
发明人： Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
IPC分类号： G06F12/00 , G06F13/28
CPC分类号： G06F13/1673 , G06F13/1689
摘要： A memory subsystem with positional read data latency that includes one or more memory modules, a memory controller and one or more memory busses is provided. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected via the memory busses.
摘要翻译：提供具有包括一个或多个存储器模块，存储器控制器和一个或多个存储器总线的位置读取数据延迟的存储器子系统。存储器控制器包括用于提供位置读取数据等待时间的指令。存储器模块和存储器控制器通过存储器总线相互连接。

13. 发明申请

US20120151131A1 MEMORY SYSTEM WITH A PROGRAMMABLE REFRESH CYCLE 有权
标题翻译：具有可编程刷新周期的存储器系统
公开(公告)号：US20120151131A1
公开(公告)日：2012-06-14
申请号：US12963797
申请日：2010-12-09
申请人： Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Vipin Patel
发明人： Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Vipin Patel
IPC分类号： G06F12/00 , G11C11/406
CPC分类号： G11C11/406 , G11C2211/4061 , G11C2211/4065
摘要： A memory system with a programmable refresh cycle including a memory device that includes a memory array of memory cells and refresh circuitry that is in communication with the memory array and with a memory controller. The refresh circuitry is configured to receive a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is programmable.
摘要翻译：一种具有可编程刷新周期的存储器系统，包括存储器件，该存储器件包括与存储器阵列和存储器控制器通信的存储器单元的存储器阵列和刷新电路。刷新电路被配置为响应于接收到刷新命令从存储器控制器接收刷新命令并且用于刷新存储器件中的多个存储器单元。响应于接收刷新命令刷新的存储器单元的数量是可编程的。

14. 发明授权

US08086936B2 Performing error correction at a memory device level that is transparent to a memory channel 有权
标题翻译：在对存储器通道透明的存储器级别执行纠错
公开(公告)号：US08086936B2
公开(公告)日：2011-12-27
申请号：US11848354
申请日：2007-08-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G11C29/00
CPC分类号： G06F11/1076 , G06F11/1048
摘要： A memory system is provided that performs error correction at a memory device level that is transparent to a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises first error correction logic provided in write logic integrated in the memory hub device. The memory hub device comprises second error correction logic provided in read logic integrated in the memory hub device. The first error correction logic and the second error correction logic performs error correction operations on data transferred between a link interface and the set of memory devices. The memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code.
摘要翻译：提供了一种在对存储器通道透明的存储器级别执行纠错的存储器系统。存储器系统包括集成在存储器模块中的存储器集线器设备和耦合到存储器集线器设备的一组存储器设备。存储器集线器设备包括集成在存储器集线器设备中的写入逻辑中提供的第一纠错逻辑。存储器集线器设备包括集成在存储器集线器设备中的读逻辑中提供的第二纠错逻辑。第一纠错逻辑和第二纠错逻辑对链接接口和该组存储器件之间传送的数据执行纠错操作。存储器集线器件通过外部存储器控制器和链路接口之间的存储器通道发送和接收数据，而没有任何纠错码。

15. 发明授权

US07930469B2 System to provide memory system power reduction without reducing overall memory system performance 失效
标题翻译：系统提供内存系统功耗降低，而不会降低整体内存系统性能
公开(公告)号：US07930469B2
公开(公告)日：2011-04-19
申请号：US12018952
申请日：2008-01-24
申请人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
发明人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G11C5/04 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F13/4243 , G11C8/18 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/159
摘要： A memory system is provided that provides memory system power reduction without reducing overall memory system performance. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an memory controller via a memory channel at a first operating frequency. The memory system also comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented. Using the asynchronous boundary, the memory channel operates at a maximum designed operating bandwidth while the second operating frequency is independently decreased to reduce power being consumed by the set of memory devices.
摘要翻译：提供了一种提供存储器系统功率降低而不降低整体存储器系统性能的存储器系统。存储器系统包括集成在存储器模块中的存储器集线器设备。存储器集线器设备包括命令队列，其经由存储器通道以第一工作频率从存储器控制器接收存储器访问命令。存储器系统还包括集成在存储器集线器设备中的存储器集线器控制器。存储器集线器控制器以第二工作频率从命令队列读取存储器访问命令。通过以第一工作频率接收存储器访问命令并且以第二工作频率读取存储器访问命令，实现异步边界。使用异步边界，存储器通道以最大设计的工作带宽工作，而第二工作频率被独立地降低以减少由该组存储器件消耗的功率。

16. 发明授权

US07925825B2 System to support a full asynchronous interface within a memory hub device 有权
标题翻译：系统支持内存集线器设备中的完整异步接口
公开(公告)号：US07925825B2
公开(公告)日：2011-04-12
申请号：US12019071
申请日：2008-01-24
申请人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
发明人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F13/4243
摘要： A memory system is provided that implements an asynchronous boundary in a memory module. The memory system comprises a memory hub device integrated in a memory module. The memory system also comprises a set of memory devices coupled to the memory hub device. The memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency. The memory system further comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented within the memory hub device of the memory module.
摘要翻译：提供了一种在存储器模块中实现异步边界的存储器系统。存储器系统包括集成在存储器模块中的存储器集线器设备。存储器系统还包括耦合到存储器集线器设备的一组存储器件。存储器集线器设备包括命令队列，其经由存储器通道以第一工作频率从外部存储器控制器接收存储器访问命令。存储器系统还包括集成在存储器集线器设备中的存储器集线器控制器。存储器集线器控制器以第二工作频率从命令队列读取存储器访问命令。通过以第一工作频率接收存储器访问命令并且以第二工作频率读取存储器访问命令，在存储器模块的存储器集线器设备内实现异步边界。

17. 发明授权

US07844771B2 System, method and storage medium for a memory subsystem command interface 失效
标题翻译：用于内存子系统命令界面的系统，方法和存储介质
公开(公告)号：US07844771B2
公开(公告)日：2010-11-30
申请号：US12059164
申请日：2008-03-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00 , G06F13/38 , G06F13/42
CPC分类号： G06F13/1684
摘要： A system for implementing a memory subsystem command interface, the system including a cascaded interconnect system including one or more memory modules, a memory controller and a memory bus. The memory controller generates a data frame that includes a plurality of commands. The memory controller and the memory module are interconnected by a packetized multi-transfer interface via the memory bus and the frame is transmitted to the memory modules via the memory bus.
摘要翻译：一种用于实现存储器子系统命令接口的系统，该系统包括包括一个或多个存储器模块，存储器控制器和存储器总线的级联互连系统。存储器控制器生成包括多个命令的数据帧。存储器控制器和存储器模块通过存储器总线通过分组化的多传输接口互连，并且帧经由存储器总线传送到存储器模块。

18. 发明申请

US20100005218A1 ENHANCED CASCADE INTERCONNECTED MEMORY SYSTEM 审中-公开
标题翻译：增强的CASCADE互连存储系统
公开(公告)号：US20100005218A1
公开(公告)日：2010-01-07
申请号：US12165816
申请日：2008-07-01
申请人： Kevin C. Gower , Paul W. Coteus , Warren E. Maule , Robert B. Tremaine
发明人： Kevin C. Gower , Paul W. Coteus , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F12/06
CPC分类号： G06F13/4234
摘要： A system, memory hub device, method and design structure for providing an enhanced cascade interconnected memory system are provided. The system includes a memory controller, a memory channel, a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and a cascade interconnection through another memory hub device, and multiple memory devices in communication with the memory controller via one or more cascade interconnected memory hub devices. The memory channel includes unidirectional downstream link segments coupled to the memory controller and operable for transferring configurable data frames. The memory channel further includes unidirectional upstream link segments coupled to the memory controller and operable for transferring data frames.
摘要翻译：提供了一种用于提供增强级联互连存储器系统的系统，存储器集线器设备，方法和设计结构。该系统包括存储器控制器，存储器通道，耦合到存储器通道的存储器集线器设备，以经由另一个存储器集线器设备的直接连接和级联互连中的一个与存储器控制器进行通信，以及与存储控制器通信的多个存储器设备存储器控制器经由一个或多个级联互连的存储器集线器设备。存储器通道包括耦合到存储器控制器并且可操作用于传输可配置数据帧的单向下游链路段。存储器通道还包括耦合到存储器控制器并且可操作用于传送数据帧的单向上游链路段。

19. 发明申请

US20100005214A1 ENHANCING BUS EFFICIENCY IN A MEMORY SYSTEM 审中-公开
标题翻译：在存储系统中提高总线效率
公开(公告)号：US20100005214A1
公开(公告)日：2010-01-07
申请号：US12165814
申请日：2008-07-01
申请人： Michael R. Trombley , Kevin C. Gower , Warren E. Maule
发明人： Michael R. Trombley , Kevin C. Gower , Warren E. Maule
IPC分类号： G06F13/42 , G06F13/36
CPC分类号： G06F13/405 , G06F13/4243 , G06F13/4256 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for enhancing bus efficiency and utilization in a memory system. The communication interface device includes a first bus interface to communicate on a high-speed bus, a second bus interface to communicate on a lower-speed bus, and clock ratio logic configurable to support multiple clock ratios between the high-speed bus and the lower-speed bus. The clock ratio logic reduces a high-speed clock frequency received at the first bus interface and outputs a reduced ratio of the high-speed clock frequency on the lower-speed bus via the second bus interface supporting variable frame sizes.
摘要翻译：一种用于提高存储系统中总线效率和利用率的通信接口设备，系统，方法和设计结构。通信接口设备包括用于在高速总线上通信的第一总线接口，用于在低速总线上进行通信的第二总线接口以及可配置为支持高速总线与低速总线之间的多个时钟比的时钟比率逻辑高速公交车时钟比率逻辑降低了在第一总线接口处接收的高速时钟频率，并且经由支持可变帧大小的第二总线接口输出低速总线上的高速时钟频率的减小的比率。

20. 发明申请

US20100003837A1 276-PIN BUFFERED MEMORY MODULE WITH ENHANCED MEMORY SYSTEM INTERCONNECT AND FEATURES 有权
标题翻译：具有增强的存储器系统的276引脚缓冲存储器模块互连和特性
公开(公告)号：US20100003837A1
公开(公告)日：2010-01-07
申请号：US12166227
申请日：2008-07-01
申请人： Karl D. Loughner , Kevin C. Gower , Charles A. Kilmer , Warren E. Maule
发明人： Karl D. Loughner , Kevin C. Gower , Charles A. Kilmer , Warren E. Maule
IPC分类号： H01R12/00
CPC分类号： G11C5/04 , H01R12/721
摘要： A memory subsystem system including a rectangular printed circuit card having a first side and a second side, a length of between 149.5 and 153.5 millimeters, and first and second ends having a width smaller than the length. The memory system also includes a first plurality of pins on the first side extending along a first edge of the card that extends the length of the card, and a second plurality of pins on the second side extending on the first edge of the card. The memory system further includes a positioning key having it center positioned on the first edge of the card and located between 84.5 and 88.5 millimeters from the first end of the card and located between 62.5 and 66.5 millimeters from the second end of the card.
摘要翻译：一种存储器子系统，包括具有第一侧和第二侧的矩形印刷电路卡，长度在149.5和153.5毫米之间，第一和第二端具有小于该长度的宽度。存储器系统还包括在第一侧上沿着延长卡的长度的卡的第一边缘延伸的第一多个销，以及在卡的第一边缘上延伸的第二侧上的第二多个销。存储系统还包括定位键，其中心位于卡的第一边缘上，并位于距离卡的第一端84.5至88.5毫米之间，并位于距卡的第二端62.5至66.5毫米之间。

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