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11. 发明授权

US07200830B2 Enhanced electrically-aligned proximity communication 有权
标题翻译：增强的电对齐邻近通信
公开(公告)号：US07200830B2
公开(公告)日：2007-04-03
申请号：US10879607
申请日：2004-06-28
申请人： Robert J. Drost , Ivan E. Sutherland , Ronald Ho
发明人： Robert J. Drost , Ivan E. Sutherland , Ronald Ho
IPC分类号： G06F17/50
CPC分类号： H01L23/48 , H01L25/0657 , H01L2225/06531 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention provides a system that facilitates capacitive inter-chip communication. During operation, the system first determines an alignment between a first semiconductor die and a second semiconductor die. Next, electrical signals are selectively routed to at least one interconnect pad in a plurality of interconnect pads based on the alignment thereby facilitating communication between the first semiconductor die and the second semiconductor die. The plurality of interconnect pads can include transmitting pads, receiving pads, and transmitting and receiving pads. The alignment may be determined continuously or at times separated by an interval, where the interval is fixed or variable. Several variations on this embodiment are provided.
摘要翻译：本发明的一个实施例提供一种便于电容芯片间通信的系统。在操作期间，系统首先确定第一半导体管芯和第二半导体管芯之间的对准。接下来，基于对准，电信号被选择性地路由到多个互连焊盘中的至少一个互连焊盘，从而便于第一半导体管芯和第二半导体管芯之间的连通。多个互连焊盘可以包括传输焊盘，接收焊盘以及发射和接收焊盘。可以连续地或有时间隔地间隔地确定对准，其中间隔是固定的或可变的。提供了该实施例的几个变型。

12. 发明授权

US07046017B1 Full-wave rectifier for capacitance measurements 有权
标题翻译：全波整流电容测量
公开(公告)号：US07046017B1
公开(公告)日：2006-05-16
申请号：US11216754
申请日：2005-08-30
申请人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
发明人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
IPC分类号： G01R27/26 , G01N27/22
CPC分类号： G01R27/2605
摘要： One embodiment of the present invention provides an electronic circuit and method for measuring a capacitance. A signal generating mechanism generates a signal having a predefined frequency and predefined low and high voltage levels on one terminal of the capacitance. The other terminal of the capacitance is coupled to a switching mechanism. The switching mechanism is set to couple the other terminal of the capacitance to a first amplifier or a second amplifier for a portion of each signal cycle thereby full-wave rectifying a transient current flowing between the two terminals in the capacitance. Outputs of the first amplifier and the second amplifier are coupled to a current measurement mechanism for measuring the current. The capacitance is determined from the measured current. Several variations on this embodiment are provided.
摘要翻译：本发明的一个实施例提供一种用于测量电容的电子电路和方法。信号发生机构在电容的一个端子上产生具有预定频率和预定义的低和高电压电平的信号。电容的另一个端子耦合到开关机构。开关机构被设置为将电容的另一个端子耦合到每个信号周期的一部分的第一放大器或第二放大器，由此对在电容中的两个端子之间流动的瞬态电流进行全波整流。第一放大器和第二放大器的输出耦合到用于测量电流的电流测量机构。电容由测量电流确定。提供了该实施例的几个变型。

13. 发明授权

US07012459B2 Method and apparatus for regulating heat in an asynchronous system 有权
标题翻译：用于调节异步系统中的热量的方法和装置
公开(公告)号：US07012459B2
公开(公告)日：2006-03-14
申请号：US10442392
申请日：2003-05-20
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： H03K17/14 , G05D23/00
CPC分类号： G05D23/1951
摘要： One embodiment of the present invention provides a system that regulates heat within an asynchronous circuit. During operation, the system monitors a temperature within the asynchronous circuit. If the temperature exceeds a threshold value, the system introduces a delay into the asynchronous circuit that causes signals to propagate more slowly through the asynchronous circuit. This causes circuit elements within the asynchronous circuit to switch less frequently and consequently causes the circuit elements to generate less heat.
摘要翻译：本发明的一个实施例提供一种调节异步电路内的热量的系统。在运行期间，系统监视异步电路内的温度。如果温度超过阈值，系统将引入延迟到异步电路，使得信号通过异步电路传播得更慢。这导致异步电路内的电路元件更不频繁地切换，并且因此导致电路元件产生较少的热量。

14. 发明授权

US06987394B1 Full-wave rectifier for capacitance measurements 有权
公开(公告)号：US06987394B1
公开(公告)日：2006-01-17
申请号：US10879608
申请日：2004-06-28
申请人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
发明人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
IPC分类号： G01R27/26
CPC分类号： G01R27/2605
摘要： One embodiment of the present invention provides an electronic circuit and method for measuring a capacitance. A signal generating mechanism generates a signal having a predefined frequency and predefined low and high voltage levels on one terminal of the capacitance. The other terminal of the capacitance is coupled to a switching mechanism. The switching mechanism is set to couple the other terminal of the capacitance to a first amplifier or a second amplifier for a portion of each signal cycle thereby full-wave rectifying a transient current flowing between the two terminals in the capacitance. Outputs of the first amplifier and the second amplifier are coupled to a current measurement mechanism for measuring the current. The capacitance is determined from the measured current. Several variations on this embodiment are provided.

15. 发明授权

US06847247B2 Jittery polyphase clock 有权
标题翻译：抖动多相时钟
公开(公告)号：US06847247B2
公开(公告)日：2005-01-25
申请号：US10304667
申请日：2002-11-25
申请人： Ian W. Jones , Ivan E. Sutherland
发明人： Ian W. Jones , Ivan E. Sutherland
IPC分类号： G06F1/06 , G06F1/10 , H03K3/00
CPC分类号： G06F1/10 , G06F1/06
摘要： A plurality of clock signal phases are distributed to a circuit and at least one jitter source is coupled between at least two selected clock phases of the plurality of clock signal phases to introduce a jitter between at least the selected two clock signal phases. In a specific embodiment, the clock distribution system provides N clock phases and, if the phases have an order, there is one jitter source provided between each of the first N−1 phases and the following phase, so that each phase has a jitter relative to each other phase. Several implementations are possible for the jitter sources, which can be noise sources or pseudo-random noise sources, depending on which is easier to design and implement in a specific clock distribution system.
摘要翻译：多个时钟信号相位被分配到电路，并且至少一个抖动源耦合在多个时钟信号相位的至少两个选定的时钟相位之间，以在至少所选择的两个时钟信号相位之间引入抖动。在具体实施例中，时钟分配系统提供N个时钟相位，并且如果相位有顺序，则在第一N-1个相位和随后的相位之间提供一个抖动源，使得每个相位具有抖动相对到彼此相位。抖动源的几种实现方式是可能的，抖动源可以是噪声源或伪随机噪声源，这取决于在特定的时钟分配系统中更易于设计和实现的抖动源。

16. 发明授权

US06769007B2 Adder circuit with a regular structure 失效
标题翻译：加法电路具有规则的结构
公开(公告)号：US06769007B2
公开(公告)日：2004-07-27
申请号：US09827569
申请日：2001-04-05
申请人： Ivan E. Sutherland , David L. Harris
发明人： Ivan E. Sutherland , David L. Harris
IPC分类号： G06F750
CPC分类号： G06F7/508
摘要： One embodiment of the present invention provides an apparatus for facilitating an addition operation between two N-bit numbers, wherein the apparatus has a regular structure. The apparatus includes a carry circuit for generating at least one carry signal for the addition operation, wherein the carry circuit includes a plurality of logic blocks organized into rows that form approximately logN successive stages of logic blocks. Each of these logic blocks provides current for at most a constant number of inputs in a successive stage of logic blocks. Additionally, within a given stage of logic blocks, outputs from multiple logic blocks are ganged together to drive a signal line that feeds multiple inputs in a successive stage of logic blocks. Furthermore, there are at most a constant number of lateral tracks in a planar layout of signal lines between the successive stages of logic blocks. Hence, the present invention can reduce layout and design effort, while producing a regularized layout that takes up a small amount of space on a semiconductor chip.
摘要翻译：本发明的一个实施例提供了一种用于促进两个N位数之间的相加操作的装置，其中该装置具有规则的结构。该装置包括用于产生用于加法运算的至少一个进位信号的进位电路，其中进位电路包括多个组合成行的逻辑块，其形成大约logN的逻辑块的连续级。这些逻辑块中的每一个在逻辑块的连续级中提供最多恒定数量的输入的电流。此外，在逻辑块的给定阶段内，来自多个逻辑块的输出被组合在一起以驱动在逻辑块的连续级中馈送多个输入的信号线。此外，在逻辑块的连续级之间的信号线的平面布局中，存在至多一定数量的横向轨道。因此，本发明可以减少布局和设计工作，同时产生在半导体芯片上占用少量空间的正规化布局。

17. 发明授权

US06710436B1 Method and apparatus for electrostatically aligning integrated circuits 有权
公开(公告)号：US06710436B1
公开(公告)日：2004-03-23
申请号：US10317481
申请日：2002-12-12
申请人： David L. Harris , Robert J. Drost , Ivan E. Sutherland
发明人： David L. Harris , Robert J. Drost , Ivan E. Sutherland
IPC分类号： B65G4907
CPC分类号： H01L24/95 , H01L23/50 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2223/6622 , H01L2224/13012 , H01L2224/81121 , H01L2224/81801 , H01L2224/95145 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01039 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/0401
摘要： One embodiment of the present invention provides a system that uses electrostatic forces to align semiconductor chips relative to each other. The system operates by fabricating a first set of conductors on the top surface of a first chip and fabricating a corresponding second set of conductors on the top surface of a second chip. To align the chips, the system electrically charges the first set of conductors and the second set of conductors. The system also places the first chip face-to-face with the second chip, so that the first set of conductors is in close proximity to the second set of conductors. This allows electrostatic forces between the first set of conductors and the second set of conductors to bring the first chip into alignment with the second chip and to hold them in place.

18. 发明授权

US06500696B2 Face to face chip 有权
公开(公告)号：US06500696B2
公开(公告)日：2002-12-31
申请号：US09969701
申请日：2001-10-02
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： H01L2144
CPC分类号： H01L23/642 , H01L23/48 , H01L25/0652 , H01L2224/16 , H01L2225/06513 , H01L2225/06531 , H01L2924/01046 , H01L2924/01079 , H01L2924/3025
摘要： An integrated circuit device includes first and second arrays of semiconductor dice. Each array of dice is arranged in face-to-face relation to the other array of dice, thus forming a lower layer of dice and an upper layer of dice. The layers are aligned so that each upper layer die straddles two or more of the lower layer dice, thus defining overlap regions. In the overlap regions, signal pads of one layer are aligned with corresponding signal pads of the other layer. The two layers are spaced apart, thus creating a capacitance-based communication path between the upper and lower layers via the signal paths.

19. 发明授权

US06496359B2 Tile array computers 有权
标题翻译：平铺阵列电脑
公开(公告)号：US06496359B2
公开(公告)日：2002-12-17
申请号：US09733241
申请日：2000-12-08
申请人： Wesley A. Clark , Ivan E. Sutherland
发明人： Wesley A. Clark , Ivan E. Sutherland
IPC分类号： G06F116
CPC分类号： G06F3/1446 , G06F19/00
摘要： A tile array computer is disclosed. A tile array computer is formed by individual tiles, each typically containing a display surface, a processor, memory, and communication devices for providing communications with adjoining tiles or the support structure upon which the tiles are placed.
摘要翻译：公开了一种瓦阵列计算机。瓦片阵列计算机由单独的瓦片形成，每个瓦片通常包含显示表面，处理器，存储器和通信设备，用于提供与相邻瓦片或铺设瓷砖的支撑结构的通信。

20. 发明授权

US5943491A Control circuit of mutual exclusion elements 失效
标题翻译：互斥元件的控制电路
公开(公告)号：US5943491A
公开(公告)日：1999-08-24
申请号：US954251
申请日：1997-10-20
申请人： Ivan E. Sutherland , Robert F. Sproull , William S. Coates
发明人： Ivan E. Sutherland , Robert F. Sproull , William S. Coates
IPC分类号： G06F9/38 , G06F15/16 , G06F15/80
CPC分类号： G06F9/3869
摘要： In certain systems where a series of stages are employed, it is desirable to control the action of a stage without possibility of interference form adjacent stages. A circuit of linked mutual exclusion elements is described which renders inactive the stages adjacent to an active stage, or inhibits action in a stage if any of its neighbors is active. This ensures that the stages adjacent to an active stage remain inactive, thereby avoiding problems associated with input events changing while an adjacent stage is active.
摘要翻译：在采用一系列级的某些系统中，期望控制一个阶段的动作，而不会产生相邻阶段的干扰。描述了链接的互斥元件的电路，其使与活动阶段相邻的阶段不活动，或者如果其邻居中的任何一个活动的话，在一个阶段中禁止动作。这确保与活动阶段相邻的阶段保持不活动，从而避免与相邻阶段有效时改变输入事件相关的问题。

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