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1. 发明授权

US5943491A Control circuit of mutual exclusion elements 失效
标题翻译：互斥元件的控制电路
公开(公告)号：US5943491A
公开(公告)日：1999-08-24
申请号：US954251
申请日：1997-10-20
申请人： Ivan E. Sutherland , Robert F. Sproull , William S. Coates
发明人： Ivan E. Sutherland , Robert F. Sproull , William S. Coates
IPC分类号： G06F9/38 , G06F15/16 , G06F15/80
CPC分类号： G06F9/3869
摘要： In certain systems where a series of stages are employed, it is desirable to control the action of a stage without possibility of interference form adjacent stages. A circuit of linked mutual exclusion elements is described which renders inactive the stages adjacent to an active stage, or inhibits action in a stage if any of its neighbors is active. This ensures that the stages adjacent to an active stage remain inactive, thereby avoiding problems associated with input events changing while an adjacent stage is active.
摘要翻译：在采用一系列级的某些系统中，期望控制一个阶段的动作，而不会产生相邻阶段的干扰。描述了链接的互斥元件的电路，其使与活动阶段相邻的阶段不活动，或者如果其邻居中的任何一个活动的话，在一个阶段中禁止动作。这确保与活动阶段相邻的阶段保持不活动，从而避免与相邻阶段有效时改变输入事件相关的问题。

2. 发明授权

US06360288B1 Method and modules for control of pipelines carrying data using pipelines carrying control signals 失效
标题翻译：使用承载控制信号的管道控制承载数据的管道的方法和模块
公开(公告)号：US06360288B1
公开(公告)日：2002-03-19
申请号：US08953767
申请日：1997-10-17
申请人： Ivan E. Sutherland , William S. Coates , Charles E. Molnar , Robert F. Sproull
发明人： Ivan E. Sutherland , William S. Coates , Charles E. Molnar , Robert F. Sproull
IPC分类号： G06F1300
CPC分类号： G06F9/3869 , G06F9/3867
摘要： A computer system is described in which control of the flow of data items in one pipeline is achieved using the values of control elements in another pipeline. Typically, each pipeline includes elements known as “places” and “paths,” and the pipelines have special connections between them by which the data present in a place in a first pipeline can be used to control the disposition of data in the second pipeline. For example, the first pipeline can control the second pipeline to enable the addition, deletion, or steering of data items in the second pipeline.
摘要翻译：描述了一种计算机系统，其中使用另一流水线中的控制元件的值来实现一条流水线中的数据项流的控制。通常，每个管道包括被称为“地点”和“路径”的元件，并且管道在它们之间具有特殊的连接，通过该特殊连接，可以使用存在于第一管道中的位置的数据来控制第二管道中的数据的布置。例如，第一流水线可以控制第二流水线，以允许第二流水线中的数据项的添加，删除或转向。

3. 发明授权

US5748539A Recursive multi-channel interface 失效
标题翻译：递归多通道接口
公开(公告)号：US5748539A
公开(公告)日：1998-05-05
申请号：US811909
申请日：1997-03-05
申请人： Robert F. Sproull , Ivan E. Sutherland
发明人： Robert F. Sproull , Ivan E. Sutherland
IPC分类号： G11C7/00 , G06F5/06
CPC分类号： G06F5/065
摘要： A multi-channel recursive interface having independent channels that can be used in, for example, multi-level memory systems is disclosed. Separate read and write command channels and read and write completion channels permit concurrent read and write operations. A memory system according to the present invention uses a write buffer to resolve read data ambiguity when concurrently reading and writing into the same memory location. With independent and asynchronous read and write channels, the interface of the present invention retains its properties even if separated from the system it interfaces by communication channels exhibiting any latency such as first in first out (FIFO) registers of arbitrary lengths. Such FIFOs can improve the throughput of the communication channels between the interface and the system it interfaces with. The recursive interface can flexibly serve many levels of memory.
摘要翻译：公开了一种具有可用于例如多级存储器系统的独立信道的多通道递归接口。单独的读写命令通道和读写完成通道允许并发读写操作。根据本发明的存储器系统在同时读取和写入相同存储器位置时使用写入缓冲器来解决读取数据模糊性。具有独立和异步的读写通道，本发明的接口即使与系统分离，也保持其特性，它通过展现任何长度的先入先出（FIFO）寄存器等任何延迟的通信通道进行接口。这样的FIFO可以提高接口与其接口的系统之间的通信信道的吞吐量。递归接口可以灵活地提供许多级别的内存。

4. 发明授权

US5572690A Cascaded multistage counterflow pipeline processor for carrying distinct data in two opposite directions 失效
标题翻译：级联多级逆流管线处理器，用于在两个相反的方向上携带不同的数据
公开(公告)号：US5572690A
公开(公告)日：1996-11-05
申请号：US468884
申请日：1995-06-06
申请人： Charles E. Molnar , Ivan E. Sutherland , Robert F. Sproull , Ian W. Jones
发明人： Charles E. Molnar , Ivan E. Sutherland , Robert F. Sproull , Ian W. Jones
IPC分类号： G06F9/38 , G06F7/00
CPC分类号： G06F7/02 , G06F9/3867
摘要： A counterflow computing pipeline including a series of similar stages is disclosed. In the basic form of the pipeline, the stages are arranged in a linear fashion and each stage in the pipeline communicates with its two adjacent stages. The flow of data elements in the pipeline is bi-directional. A first data stream of data elements flows in a first direction from stage to stage in the pipeline. A second data stream of data elements flows from stage to stage in the pipeline in a second direction counter to the first direction. Circuitry at each stage is provided so that every data element flowing in the first direction meets each and every data element that it passes flowing in the second direction. According to various embodiments of the invention, when two data elements meet at a stage, circuitry may be provided to compare the data elements, copy data from one data element to the other, or otherwise, cause the data elements to interact. The counterflow pipeline may be either synchronous or asynchronous, and may be used for a variety of applications in signal processing, associative memory, and computer architectures.
摘要翻译：公开了一种包括一系列类似阶段的逆流计算流水线。在流水线的基本形式中，阶段以线性方式布置，管道中的每个阶段与其两个相邻的阶段相通。流水线中的数据元素流是双向的。数据元素的第一数据流在流水线中从一级到另一级沿第一方向流动。数据元素的第二数据流在与第一方向相反的第二方向上在流水线中从一级流到另一级。提供每个级的电路，使得沿第一方向流动的每个数据元素满足其沿第二方向流过的每个数据元素。根据本发明的各种实施例，当两个数据元件在一个阶段相遇时，可以提供电路以比较数据元素，将数据从一个数据元素复制到另一个数据元素，或以其他方式使数据元素相互作用。逆流管线可以是同步或异步的，并且可以用于信号处理，关联存储器和计算机体系结构中的各种应用。

5. 发明授权

US5600848A Counterflow pipeline processor with instructions flowing in a first direction and instruction results flowing in the reverse direction 失效
标题翻译：逆流管线处理器，其指令沿第一方向流动，指令结果沿相反方向流动
公开(公告)号：US5600848A
公开(公告)日：1997-02-04
申请号：US477533
申请日：1995-06-07
申请人： Robert F. Sproull , Ivan E. Sutherland
发明人： Robert F. Sproull , Ivan E. Sutherland
IPC分类号： G06F9/38 , G06F13/00
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/384 , G06F9/3867
摘要： A general purpose computer capable of executing instructions of the type commonly found in multiple-address register-oriented instruction sets such as the SPARC instruction set is built from a counterflow pipeline. Communication in the pipeline flows both ways between adjacent stages and different stages in the pipeline are able to perform different instructions. Instructions flow through the pipeline in one direction, ("up") and the answers computed by previous instructions, called "results," flow in the other direction, ("down"). Comparison circuits in each stage of the pipeline permit instructions to select and copy the data values they need from the downward flowing stream of previously computed results. The comparison circuits also remove from the downward flowing stream previously computed results that would be rendered obsolete by execution of the present instruction.
摘要翻译：能够执行通常在诸如SPARC指令集的多地址寄存器定向指令集中发现的类型的指令的通用计算机从逆流管线构建。管道中的通信在相邻阶段之间流动，管道中的不同阶段能够执行不同的指令。指令沿着一个方向流过管道（“向上”），由先前的指令计算的答案称为“结果”，沿着另一个方向（“向下”）流动。流水线的每个阶段的比较电路允许指令从先前计算结果的向下流动的流中选择和复制他们需要的数据值。比较电路还从向下流动的流中去除先前计算的结果，这些结果将通过执行本指令而过时。

6. 发明授权

US06600325B2 Method and apparatus for probing an integrated circuit through capacitive coupling 有权
公开(公告)号：US06600325B2
公开(公告)日：2003-07-29
申请号：US09778622
申请日：2001-02-06
申请人： William S. Coates , Robert J. Bosnyak , Ivan E. Sutherland
发明人： William S. Coates , Robert J. Bosnyak , Ivan E. Sutherland
IPC分类号： G01R3108
CPC分类号： G01R31/303 , G01R31/3025 , G01R31/312
摘要： One embodiment of the present invention provides a system for capacitively probing electrical signals within an integrated circuit. This system operates by placing a probe conductor in close proximity to, but not touching, a target conductor within the integrated circuit. In this position, the probe conductor and the target conductor form a capacitor that stores a charge between the probe conductor and the target conductor. Next, the system detects a change in a probe voltage on the probe conductor caused by a change in a target voltage on the target conductor, and then determines a logic value for the target conductor based on the change in the probe voltage. In one embodiment of the present invention, determining the logic value for the target conductor involves, determining a first value if the probe voltage decreases, and determining a second value if the probe voltage increases.

7. 发明授权

US07994501B2 Method and apparatus for electronically aligning capacitively coupled mini-bars 有权
标题翻译：用于电容对齐电容耦合迷你条的方法和装置
公开(公告)号：US07994501B2
公开(公告)日：2011-08-09
申请号：US12114404
申请日：2008-05-02
申请人： Robert J. Drost , Ivan E. Sutherland , William S. Coates
发明人： Robert J. Drost , Ivan E. Sutherland , William S. Coates
IPC分类号： H01L23/58 , H01L29/10
CPC分类号： H01L25/0657 , H01L23/48 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/00011 , H01L2924/00014 , H01L2924/01067 , H01L2224/0401
摘要： Embodiments of the present invention provide a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system selects a group of transmitter mini-bars on the first chip to form a transmitter bit position and selects a group of receiver mini-bars on the second chip to form a receiver bit position. The system then associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip. In this way, the system allows data signals transmitted by the mini-bars within a transmitter bit position on the first chip to be collectively received by the mini-bars within an associated receiver bit position on the second chip.
摘要翻译：本发明的实施例提供了一种系统，其将面对面地定位在不同半导体芯片上的迷你条电子对准以便于通过电容耦合来促进半导体芯片之间的通信。在操作期间，系统在第一芯片上选择一组发射机迷你条来形成发射机位位置，并在第二芯片上选择一组接收器迷你条来形成接收器位位置。然后，系统将第一芯片上的发送器位置与第二芯片上的接收器位置相关联。以这种方式，系统允许由第一芯片上的发送器位置内的迷你条发送的数据信号由第二芯片上相关联的接收器位位置内的迷你条集中接收。

8. 发明授权

US06741616B1 Switch fabric for asynchronously transferring data within a circuit 有权
标题翻译：交换结构，用于在电路内异步传输数据
公开(公告)号：US06741616B1
公开(公告)日：2004-05-25
申请号：US09685009
申请日：2000-10-05
申请人： Ivan E. Sutherland , William S. Coates , Ian W. Jones
发明人： Ivan E. Sutherland , William S. Coates , Ian W. Jones
IPC分类号： H04J304
CPC分类号： H04L12/4625 , H04L49/101
摘要： One embodiment of the present invention provides a system that facilitates asynchronously routing data within a circuit. This system includes a data destination horn, for routing data from a trunk line to a plurality of destinations. This data destination horn includes a plurality of one-to-many switching elements organized into a tree of at least one level that fans out from the trunk line to the plurality of destinations. It also includes a plurality of memory elements for storing data in transit between the plurality of one-to-many switching elements. An asynchronous control structure is coupled to the data destination horn, and is configured to control the propagation of data through the data destination horn, so that when a given data item appears at an input of a memory element, the given data item is asynchronously latched into the memory element as soon space becomes available in the memory element without having to wait for a clock signal. One embodiment of the present invention additionally includes a data source funnel, for routing data from a plurality of sources into the trunk line. This data source funnel includes a plurality of many-to-one switching elements organized into a tree of at least one level that fans in from the plurality of sources to into the trunk line. It also includes a plurality of funnel memory elements for storing data in transit between the plurality of many-to-one switching elements. Moreover, the asynchronous control structure is additionally configured to control propagation of data through the data source funnel.
摘要翻译：本发明的一个实施例提供一种便于在电路内异步路由数据的系统。该系统包括数据目的地喇叭，用于将数据从中继线路由到多个目的地。该数据目的地喇叭包括组合成至少一个级别的树的多个一对多交换元件，其从干线到多个目的地扇出。它还包括用于存储在多个一对多交换元件之间传输的数据的多个存储元件。异步控制结构被耦合到数据目标喇叭，并且被配置为控制数据通过数据目的地喇叭的传播，使得当给定的数据项出现在存储器元件的输入端时，给定的数据项被异步锁存随着空间在存储器元件中可用，而不必等待时钟信号，就进入存储元件。本发明的一个实施例还包括数据源漏斗，用于将数据从多个源路由到干线。该数据源漏斗包括多个多对一的开关元件，其组织成至少一个级别的树，该多个级别的风扇从多个源中进入干线。它还包括多个漏斗存储器元件，用于存储在多个多对一开关元件之间的传输中的数据。此外，异步控制结构还被配置为控制数据通过数据源漏斗的传播。

9. 发明授权

US6085316A Layered counterflow pipeline processor with anticipatory control 失效
标题翻译：具有预期控制的分层逆流管线处理器
公开(公告)号：US6085316A
公开(公告)日：2000-07-04
申请号：US123587
申请日：1998-07-28
申请人： Ivan E. Sutherland , Charles E. Molnar, deceased , Ian W. Jones , William S. Coates , Jon Lexau
发明人： Ivan E. Sutherland , Charles E. Molnar, deceased , Ian W. Jones , William S. Coates , Jon Lexau
IPC分类号： G06F9/38 , G06F15/78 , G06F15/80 , G06F9/28 , G06F13/40
CPC分类号： G06F9/3873 , G06F15/8007 , G06F15/8053 , G06F9/3867
摘要： A layered counterflow pipeline structure is described in which sub-tasks performed at each stage in a counterflow pipeline processor are separated into different layers. As words flow through the counterflow pipeline processor, they are divided into partial words which are supplied to the different layers, GET, CHECK and PROCESS, for appropriate handling by that portion of each stage. In the GET layer, partial words passing through each stage are analyzed to determine whether they constitute an encounter pair. In the CHECK layer a determination is made as to whether the word selected by the GET layer requires further modification. Finally, in the PROCESS layer operations are performed on the words themselves based upon control messages from the other layers. The layers of the processor communicate with each other using suitable communication paths such as First In First Out registers.
摘要翻译：描述了分层逆流管线结构，其中在逆流管线处理器中的每个阶段执行的子任务被分成不同的层。当文字流过逆流流水线处理器时，它们被分成供应给不同层的部分单词，GET，CHECK和PROCESS，以便每个阶段的该部分进行适当的处理。在GET层中，分析通过每个阶段的部分单词，以确定它们是否构成遇到对。在CHECK层中，确定由GET层选择的单词是否需要进一步修改。最后，在PROCESS层中，基于来自其他层的控制消息对单词本身执行操作。处理器的层使用诸如先进先出寄存器之类的合适的通信路径彼此通信。

10. 发明申请

US20080208521A1 METHOD AND APPARATUS FOR ELECTRONICALLY ALIGNING CAPACITIVELY COUPLED MNI-BARS 有权
标题翻译：电子联结电容式MNI-BARS的方法与装置
公开(公告)号：US20080208521A1
公开(公告)日：2008-08-28
申请号：US12114404
申请日：2008-05-02
申请人： Robert J. Drost , Ivan E. Sutherland , William S. Coates
发明人： Robert J. Drost , Ivan E. Sutherland , William S. Coates
IPC分类号： G01C9/00
CPC分类号： H01L25/0657 , H01L23/48 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/00011 , H01L2924/00014 , H01L2924/01067 , H01L2224/0401
摘要： Embodiments of the present invention provide a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system selects a group of transmitter mini-bars on the first chip to form a transmitter bit position and selects a group of receiver mini-bars on the second chip to form a receiver bit position. The system then associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip. In this way, the system allows data signals transmitted by the mini-bars within a transmitter bit position on the first chip to be collectively received by the mini-bars within an associated receiver bit position on the second chip.
摘要翻译：本发明的实施例提供了一种系统，其将面对面地定位在不同半导体芯片上的迷你条电子对准以便于通过电容耦合来促进半导体芯片之间的通信。在操作期间，系统在第一芯片上选择一组发射机迷你条来形成发射机位位置，并在第二芯片上选择一组接收器迷你条来形成接收器位位置。然后，系统将第一芯片上的发送器位置与第二芯片上的接收器位置相关联。以这种方式，系统允许由第一芯片上的发送器位置内的迷你条发送的数据信号由第二芯片上相关联的接收器位位置内的迷你条集中接收。

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