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11. 发明授权

US08201127B1 Method and apparatus for reducing clock signal power consumption within an integrated circuit 有权
标题翻译：用于降低集成电路内的时钟信号功率消耗的方法和装置
公开(公告)号：US08201127B1
公开(公告)日：2012-06-12
申请号：US12273407
申请日：2008-11-18
申请人： Qiang Wang , Jason H. Anderson , Subodh Gupta
发明人： Qiang Wang , Jason H. Anderson , Subodh Gupta
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5054 , G06F2217/62 , G06F2217/78 , G06F2217/84
摘要： A method is provided whereby a placement-based cost function is utilized to minimize leakage and dynamic power that is consumed by clock networks implemented within integrated circuits (ICs) such as field programmable gate arrays (FPGAs). An initial placement of clock signal loads is analyzed to determine whether an alternative placement of clock signal loads results in the reduction of the usage of vertical clock spines, or equivalently, the optimization of the cost function. Several desirable characteristics are obtained through strategic clock signal load placement within the FPGA in accordance with the cost function. First, the number of clock regions spanned by a particular clock signal is minimized. Second, interconnect capacitance within the clock region is also minimized. By minimizing the total capacitance of a particular clock network implemented within a clock region, the leakage and dynamic power consumed by the clock network within the clock region is also minimized.
摘要翻译：提供了一种方法，由此利用基于放置的成本函数来最小化在诸如现场可编程门阵列（FPGA）的集成电路（IC）内实现的时钟网络所消耗的泄漏和动态功率。分析时钟信号负载的初始放置，以确定时钟信号负载的替代放置是否导致垂直时钟棘轮的使用的减少，或等效地降低成本函数的优化。根据成本函数，可以通过FPGA内的战略时钟信号负载放置来获得几个理想的特性。首先，由特定时钟信号跨越的时钟区域的数量被最小化。第二，时钟区域内的互连电容也被最小化。通过最小化在时钟区域内实现的特定时钟网络的总电容，时钟区域内的时钟网络所消耗的泄漏和动态功率也被最小化。

12. 发明授权

US06983439B1 Unified placer infrastructure 有权
标题翻译：统一铺设基础设施
公开(公告)号：US06983439B1
公开(公告)日：2006-01-03
申请号：US10283638
申请日：2002-10-29
申请人： James L. Saunders , Krishnan Anandh , Guenter Stenz , Sudip K. Nag , Jason H. Anderson
发明人： James L. Saunders , Krishnan Anandh , Guenter Stenz , Sudip K. Nag , Jason H. Anderson
IPC分类号： G06F9/45
CPC分类号： G06F17/5072
摘要： Method and apparatus are described for a placer system for placing design objects onto an arrayed architecture, such as a programmable logic device including an FPGA. More particularly, a placer interface is described for communicating with a placer core. The placer interface receives information from external entities, and unifies and generalizes this information for the placer core. The external entities comprise different representations of architecture, design, device, constraints and algorithm-dictated placer-movable objects.
摘要翻译：描述了用于将设计对象放置在诸如包括FPGA的可编程逻辑器件的阵列架构上的放置器系统的方法和装置。更具体地，描述了用于与放置器芯通信的放置器接口。放置接口从外部实体接收信息，并统一并概括了该信息的堆栈核心。外部实体包括架构，设计，设备，约束和算法规定的可移动物体的不同表示。

13. 发明授权

US06289496B1 Placement of input-output design objects into a programmable gate array supporting multiple voltage standards 失效
标题翻译：将输入输出设计对象放置在支持多个电压标准的可编程门阵列中
公开(公告)号：US06289496B1
公开(公告)日：2001-09-11
申请号：US09107022
申请日：1998-06-29
申请人： Jason H. Anderson , James L. Saunders , Madabhushi V. R. Chari , Sudip K. Nag , Rajeev Jayaraman
发明人： Jason H. Anderson , James L. Saunders , Madabhushi V. R. Chari , Sudip K. Nag , Rajeev Jayaraman
IPC分类号： G06F1750
CPC分类号： H03K19/17744 , G06F17/5072 , H03K19/17788
摘要： A method and apparatus for placement into a programmable gate array of input-output (I/O) design objects having different voltage standards. The programmable gate array has a plurality of sites arranged into banks supporting interfaces with a plurality of different input and output voltage standards. In an example embodiment, I/O design objects are placed into IOBs of the programmable gate array by first performing simulated annealing that considers conflicts between design object voltage standards as placed into the IOBs. Then, a bipartite matching is performed using placement results from simulated annealing. Finally, if the bipartite matching does not produce a feasible placement, standards are assigned to the banks based on the previous placement results, and the bipartite matching process is repeated.
摘要翻译：一种用于放置到具有不同电压标准的输入输出（I / O）设计对象的可编程门阵列中的方法和装置。可编程门阵列具有多个位置，其布置成支撑具有多个不同输入和输出电压标准的接口的支架。在示例性实施例中，I / O设计对象通过首先执行模拟退火而被放置在可编程门阵列的IOB中，该模拟退火考虑了放置在IOB中的设计对象电压标准之间的冲突。然后，使用模拟退火的放置结果进行二分相匹配。最后，如果二分配匹配不能产生可行的布局，则基于先前的布局结果将标准分配给银行，并重复二分配匹配过程。

14. 发明授权

US07653891B1 Method of reducing power of a circuit 有权
标题翻译：降低电路功率的方法
公开(公告)号：US07653891B1
公开(公告)日：2010-01-26
申请号：US11710096
申请日：2007-02-23
申请人： Jason H. Anderson , Manoj Chirania , Subodh Gupta , Philip D. Costello
发明人： Jason H. Anderson , Manoj Chirania , Subodh Gupta , Philip D. Costello
IPC分类号： H03K17/693
CPC分类号： H03K19/17784 , H03K17/005 , H03K17/16 , H03K19/00346 , H03K19/1731
摘要： A method of reducing power of a circuit is described. The method includes determining at least one unused selection input associated with stages of a multiplexer tree; pulling the at least one unused selection input to a constant value; and assigning predetermined values to unused data inputs of the multiplexer tree associated with the at least one unused selection input.
摘要翻译：描述了一种降低电路功率的方法。该方法包括确定与复用器树的阶段相关联的至少一个未使用的选择输入; 将至少一个未使用的选择输入拉至恒定值; 以及将预定值分配给与所述至少一个未使用的选择输入相关联的多路复用器树的未使用的数据输入。

15. 发明授权

US07555734B1 Processing constraints in computer-aided design for integrated circuits 有权
标题翻译：集成电路计算机辅助设计中的处理约束
公开(公告)号：US07555734B1
公开(公告)日：2009-06-30
申请号：US11810442
申请日：2007-06-05
申请人： Qiang Wang , Rajat Aggarwal , Jason H. Anderson
发明人： Qiang Wang , Rajat Aggarwal , Jason H. Anderson
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5054
摘要： A computer-implemented method of performing a Computer-Aided Design (CAD) flow on a circuit design for a programmable logic device (PLD) can include inserting a preprocessing task into the CAD flow prior to a selected task that does not recognize a constraint, wherein the preprocessing task introduces a modification into the circuit design according to the constraint. The circuit design including the modification can be processed through the selected task of the CAD flow. A reversal task can also be inserted into the CAD flow, wherein the reversal task removes the modification introduced into the circuit design by the preprocessing task. The method further can include processing the circuit design through at least one other task of the CAD flow and outputting the processed circuit design.
摘要翻译：在可编程逻辑设备（PLD）的电路设计上执行计算机辅助设计（CAD）流程的计算机实现的方法可以包括在不识别约束的所选择的任务之前将预处理任务插入到CAD流程中，其中所述预处理任务根据所述约束将修改引入到所述电路设计中。包括修改的电路设计可以通过CAD流程的选定任务进行处理。还可以将反转任务插入到CAD流程中，其中反转任务通过预处理任务去除引入到电路设计中的修改。该方法还可以包括通过CAD流程的至少一个其他任务处理电路设计并输出经处理的电路设计。

16. 发明授权

US07143380B1 Method for application of network flow techniques under constraints 有权
标题翻译：网络流技术在约束条件下的应用方法
公开(公告)号：US07143380B1
公开(公告)日：2006-11-28
申请号：US10215979
申请日：2002-08-08
申请人： Jason H. Anderson , Sudip K. Nag , Guenter Stenz , Srinivasan Dasasathyan
发明人： Jason H. Anderson , Sudip K. Nag , Guenter Stenz , Srinivasan Dasasathyan
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/509 , G06F2217/06
摘要： Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.
摘要翻译：公开了网络流技术对约束优化问题的应用。约束的存在可能导致不可行的解决方案。可以通过改变网络结构和/或相关参数的迭代过程来消除不可行的解决方案。公开了本发明在集成电路中放置三态缓冲器和时钟的具体应用。

17. 发明授权

US07618533B2 Filter system for an automobile engine 失效
公开(公告)号：US07618533B2
公开(公告)日：2009-11-17
申请号：US11545653
申请日：2006-10-09
申请人： Jason H. Anderson , Cristy Anderson
发明人： Jason H. Anderson , Cristy Anderson
IPC分类号： B01D35/02 , B01D27/00
CPC分类号： B01D29/35 , B01D35/02 , B01D35/30 , B01D2201/309
摘要： A filter system for use in an automobile engine includes a filter unit fluidically interposed between a fluid pump of the engine and a heater core of the engine. The filter unit includes an inner core removably mounted in an outer case. The inner core includes a fluid permeable wall which filters fluid as the fluid passes through the filter unit.

18. 发明授权

US07603646B1 Method and apparatus for power optimization using don't care conditions of configuration bits in lookup tables 有权
标题翻译：用于功率优化的方法和设备使用查找表中的配置位的无关条件
公开(公告)号：US07603646B1
公开(公告)日：2009-10-13
申请号：US11820894
申请日：2007-06-21
申请人： Tetse Jang , Kevin Chung , Jason H. Anderson , Qiang Wang , Subodh Gupta
发明人： Tetse Jang , Kevin Chung , Jason H. Anderson , Qiang Wang , Subodh Gupta
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/78
摘要： Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, one or more configuration bits that have don't care conditions are identified for a LUT block of a design. A dynamic power state for a subset of a first level of logic devices in the LUT block is determined as a function of each identified configuration bit that has a don't care condition. A dynamic power state for a subset of a second level of logic devices is determined as a function of the determined power state for the first level of logic devices. A respective value for each identified configuration bit of the LUT is selected in response to the determined dynamic power states. The respective value is placed into the design for each identified configuration bit.
摘要翻译：公开了用于生成电子电路设计的实现的各种方法。在一种方法中，为设计的LUT块识别出不关心条件的一个或多个配置位。 LUT块中的第一级逻辑器件的子集的动态功率状态被确定为具有无关紧要条件的每个识别的配置位的函数。根据第一级逻辑器件的确定的功率状态来确定第二级逻辑器件的子集的动态功率状态。响应于确定的动态功率状态来选择LUT的每个识别的配置位的相应值。相应的值被放置在每个识别的配置位的设计中。

19. 发明授权

US06871336B1 Incremental placement of design objects in integrated circuit design 有权
标题翻译：设计对象在集成电路设计中的增量放置
公开(公告)号：US06871336B1
公开(公告)日：2005-03-22
申请号：US10273448
申请日：2002-10-17
申请人： Jason H. Anderson
发明人： Jason H. Anderson
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An incremental placement method uses a set of connections to optimize and a set of movable design objects. The movable design objects are unplaced. A plurality of anchoring connections is associated with the movable design objects. A set of weights is associated with the set of connections to optimize and the plurality of anchoring connections. An objective function is constructed using the set of connections to optimize, the plurality of anchoring connections, and the set of weights. The objective function is minimized to obtain a placement of the movable design objects.
摘要翻译：增量放置方法使用一组连接进行优化和一组可移动设计对象。可移动设计对象未放置。多个锚定连接与可移动设计对象相关联。一组权重与要优化的连接集合和多个锚定连接相关联。使用一组连接来优化，多个锚定连接和一组权重来构建目标函数。目标函数被最小化以获得可移动设计对象的放置。

20. 发明授权

US07735047B1 Method for technology mapping considering boolean flexibility 有权
标题翻译：考虑布尔灵活性的技术映射方法
公开(公告)号：US07735047B1
公开(公告)日：2010-06-08
申请号：US11998337
申请日：2007-11-29
申请人： Jason H. Anderson , Qiang Wang
发明人： Jason H. Anderson , Qiang Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/505
摘要： Disclosed are processor-implemented methods for technology mapping a logic network onto programmable logic resources of a programmable logic device. The methods include determining respective Boolean flexibility values for a plurality of functionally equivalent mappings of the logic network onto the programmable logic resources, selecting one of the mappings as a function of the respective Boolean flexibility values, and storing the selected mapping.
摘要翻译：公开了用于将逻辑网络映射到可编程逻辑器件的可编程逻辑资源的技术的处理器实现的方法。所述方法包括将逻辑网络的多个功能等效映射的各个布尔灵活性值确定到可编程逻辑资源上，根据各自的布尔灵活性值选择一个映射，并存储所选择的映射。

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