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11. 发明申请

US20120057163A1 METHOD FOR FORMING A NANOSTRUCTURE PENETRATING A LAYER 有权
标题翻译：形成一层纳米结构的方法
公开(公告)号：US20120057163A1
公开(公告)日：2012-03-08
申请号：US13157154
申请日：2011-06-09
申请人： Kai Cheng , Pol Van Dorpe , Liesbet Lagae , Gustaaf Borghs , Chang Chen
发明人： Kai Cheng , Pol Van Dorpe , Liesbet Lagae , Gustaaf Borghs , Chang Chen
IPC分类号： H01L31/00 , H01L31/18 , G01N21/55 , B82Y40/00 , B82Y99/00
CPC分类号： B82Y15/00 , B82Y20/00 , B82Y40/00 , G01N21/554 , G01N21/648 , G01N21/658 , G01N33/48721 , G01N2021/653 , Y10S977/724 , Y10S977/924
摘要： A method for forming a nanostructure penetrating a layer and the device made thereof is disclosed. In one aspect, the device has a substrate, a layer present thereon, and a nanostructure penetrating the layer. The nanostructure defines a nanoscale passageway through which a molecule to be analyzed can pass through. The nanostructure has, in cross-sectional view, a substantially triangular shape. This shape is particularly achieved by growth of an epitaxial layer having crystal facets defining tilted sidewalls of the nanostructure. It is highly suitably for use for optical characterization of molecular structure, particularly with surface plasmon enhanced transmission spectroscopy.
摘要翻译：公开了一种形成穿透层的纳米结构的方法及其制造的器件。在一个方面，该装置具有基底，存在于其上的层和穿透该层的纳米结构。纳米结构定义了一个纳米尺度的通道，待分析的分子通过该通道通过。纳米结构在横截面图中具有基本上三角形的形状。通过具有限定纳米结构的倾斜侧壁的晶面的外延层的生长，特别地实现了该形状。它非常适合用于分子结构的光学表征，特别是用于表面等离子体增强透射光谱。

12. 发明授权

US07996625B2 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture 有权
标题翻译：用于减少高速缓存一致多节点架构中的存储器延迟的方法和装置
公开(公告)号：US07996625B2
公开(公告)日：2011-08-09
申请号：US11790989
申请日：2007-04-30
申请人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
发明人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0817 , G06F12/0862 , G06F2212/2542 , G06F2212/507
摘要： A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.
摘要翻译：一种用于减少多节点架构中的存储器延迟的方法。在一个实施例中，在确定高速缓存一致性协议的结果之前，向家庭节点发出推测性读请求。家庭节点启动对存储器的读取以完成推测性读取请求。高速缓存一致性协议的结果可以由相干代理确定，以在发布推测读请求之后解析高速缓存一致性。

13. 发明授权

US07991963B2 In-memory, in-page directory cache coherency scheme 有权
标题翻译：内存中，页内目录缓存一致性方案
公开(公告)号：US07991963B2
公开(公告)日：2011-08-02
申请号：US12006326
申请日：2007-12-31
申请人： Ian M. Steiner , Zhong-Ning George Cai , Saurabh Tiwari , Kai Cheng
发明人： Ian M. Steiner , Zhong-Ning George Cai , Saurabh Tiwari , Kai Cheng
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： In an embodiment, the method provides receiving a memory access request for a demanded cache line from a processor of a plurality of processors; accessing coherency information associated with the demanded cache line from a memory unit by bringing in from a memory page in which the demanded cache line is stored, the memory page also including a directory line having coherency information corresponding to the demanded cache line; reading data associated with the demanded cache line in accordance with the coherency information; and returning the data to the processor.
摘要翻译：在一个实施例中，该方法提供从多个处理器的处理器接收对所请求的高速缓存行的存储器访问请求; 通过从其中存储所请求的高速缓存线的存储器页引入来存储与所请求的高速缓存行相关联的一致性信息，所述存储器页面还包括具有与所请求的高速缓存行对应的一致性信息的目录行; 根据一致性信息读取与所请求的高速缓存线相关联的数据; 并将数据返回到处理器。

14. 发明申请

US20110101370A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110101370A1
公开(公告)日：2011-05-05
申请号：US12916346
申请日：2010-10-29
申请人： Kai Cheng , Stefan Degroote
发明人： Kai Cheng , Stefan Degroote
IPC分类号： H01L29/66 , H01L21/20
CPC分类号： H01L21/02389 , H01L21/02422 , H01L21/0245 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L29/0649 , H01L29/2003 , H01L29/66477 , H01L29/7786
摘要： A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions.
摘要翻译：公开了一种半导体器件及其制造方法。一方面，该器件在半导体衬底的顶部上包括半导体衬底和GaN型层叠层。 GaN型层堆叠具有至少一个缓冲层，第一有源层和第二有源层。有源器件区可以在第一和第二有源层的界面处被定义。半导体衬底存在于绝缘层上，并被图案化以根据预定图案限定沟槽，其包括位于有源器件区域下方的至少一个沟槽。沟槽从绝缘层延伸到GaN型层堆叠的至少一个缓冲层中，并且在至少一个缓冲层内长满，从而获得第一和第二活性层至少在活性物质内连续设备区域。

15. 发明授权

US07930464B2 Scalable memory and I/O multiprocessor systems 有权
标题翻译：可扩展内存和I / O多处理器系统
公开(公告)号：US07930464B2
公开(公告)日：2011-04-19
申请号：US12549491
申请日：2009-08-28
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

16. 发明申请

US20090171875A1 SYSTEMS, METHODS AND APPARATUSES FOR RANK COORDINATION 有权
标题翻译： RANK协调的系统，方法和设备
公开(公告)号：US20090171875A1
公开(公告)日：2009-07-02
申请号：US11965955
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner
IPC分类号： G06N5/02
CPC分类号： G06N5/02
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed.
摘要翻译：本发明的实施例一般涉及用于秩协调的系统，方法和装置。在一些实施例中，主机包括秩协调逻辑。秩协调逻辑可以包括性能测量逻辑，以至少部分地基于存储器通道的性能来测量存储器通道的性能和停留周期控制逻辑以选择驻留时间的长度。描述和要求保护其他实施例。

17. 发明授权

US07444479B2 Fully buffered DIMM read data substitution for write acknowledgement 失效
标题翻译：全缓冲DIMM读取数据替代写入确认
公开(公告)号：US07444479B2
公开(公告)日：2008-10-28
申请号：US11321322
申请日：2005-12-28
申请人： James W. Alexander , Rajat Agarwal , Bruce A. Christenson , Kai Cheng
发明人： James W. Alexander , Rajat Agarwal , Bruce A. Christenson , Kai Cheng
IPC分类号： G06F12/16
CPC分类号： G06F13/4234 , G06F13/1673
摘要： A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.
摘要翻译：内存控制器使用一种方案来从重放队列中退出两个条目，这是由于单个无错误的响应。有利地，重放队列中的条目可以比常规系统更早地退出，从而最小化重播队列的大小。

18. 发明申请

US20080109624A1 Multiprocessor system with private memory sections 审中-公开
标题翻译：具有专用内存段的多处理器系统
公开(公告)号：US20080109624A1
公开(公告)日：2008-05-08
申请号：US11592771
申请日：2006-11-03
申请人： Jeffrey D. Gilbert , Stephen R. Wheat , Kai Cheng , Rajesh S. Pamujula
发明人： Jeffrey D. Gilbert , Stephen R. Wheat , Kai Cheng , Rajesh S. Pamujula
IPC分类号： G06F12/08
CPC分类号： G06F12/0284 , G06F12/082 , G06F12/0831
摘要： A system and method for providing multiprocessors with private memory are described. In one embodiment, a first chip couples to a plurality of processor chips. In one embodiment, the first chip includes memory management circuitry and system coherency circuitry. In one embodiment, the memory management circuitry assigns segments of memory to be system memory sections or private memory sections within a segment. In one embodiment, the system coherency circuitry maintains coherence of entries in the system memory.
摘要翻译：描述了一种用于向多处理器提供专用存储器的系统和方法。在一个实施例中，第一芯片耦合到多个处理器芯片。在一个实施例中，第一芯片包括存储器管理电路和系统一致性电路。在一个实施例中，存储器管理电路将存储器的段分配为段内的系统存储器部分或专用存储器部分。在一个实施例中，系统一致性电路保持系统存储器中条目的一致性。

19. 发明申请

US20070239941A1 Preselecting E/M line replacement technique for a snoop filter 有权
标题翻译：为窥探过滤器预选E / M线更换技术
公开(公告)号：US20070239941A1
公开(公告)日：2007-10-11
申请号：US11394503
申请日：2006-03-31
申请人： Lily Looi , Liqun Cheng , Kai Cheng , Faye Briggs
发明人： Lily Looi , Liqun Cheng , Kai Cheng , Faye Briggs
IPC分类号： G06F13/28
CPC分类号： G06F12/082 , G06F12/0831 , G06F12/121
摘要： A snoop filter maintains data coherency information for multiple caches in a multi-processor system. When a new request for a memory line arrives, an entry of the snoop filter is selected for replacement if there is no available slot in the snoop filter to accommodate the new request. The selected entry is among the entries predicted to be short-lived based on a coherency state. An invalidation message is sent to the one of the caches with which the selected entry is associated.
摘要翻译：监听过滤器在多处理器系统中维护多个高速缓存的数据一致性信息。当存储线路的新请求到达时，如果窥探过滤器中没有可用的插槽以容纳新的请求，则选择窥探过滤器的条目进行替换。所选条目是基于一致性状态预测为短命的条目之一。将无效消息发送到与所选条目关联的缓存中的一个缓存。

20. 发明授权

US07093079B2 Snoop filter bypass 有权
标题翻译：窥探过滤器旁路
公开(公告)号：US07093079B2
公开(公告)日：2006-08-15
申请号：US10323200
申请日：2002-12-17
申请人： Tuan M. Quach , Lily Pao Looi , Kai Cheng
发明人： Tuan M. Quach , Lily Pao Looi , Kai Cheng
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/082
摘要： Machine-readable media, methods, and apparatus are described for processing coherent requests of a computing device comprising multiple cache nodes. In some embodiments, a coherent switch may receive from a requesting cache node a coherent request for a line of memory. The coherent switch may further issue snoop requests to one or more non-requesting cache nodes based upon whether a snoop filter bypass mode is enabled. In particular, the coherent switch when not in snoop filter bypass mode may obtain coherency data from a snoop filter and may issue snoop requests to zero or more non-requesting cache nodes based upon the coherency data obtained from the snoop filter. Further, the coherent switch when in snoop filter bypass mode may bypass the snoop filter and may issue snoop requests to all non-requesting cache agents.
摘要翻译：描述了用于处理包括多个高速缓存节点的计算设备的相干请求的机器可读介质，方法和装置。在一些实施例中，相干开关可以从请求的高速缓存节点接收对一行存储器的相干请求。基于是否启用窥探过滤器旁路模式，相干交换机可以进一步向一个或多个非请求高速缓存节点发出窥探请求。特别地，当不在窥探过滤器旁路模式时，相干开关可以从窥探过滤器获得一致性数据，并且可以基于从窥探过滤器获得的一致性数据向0个或更多个非请求缓存节点发出窥探请求。此外，在窥探过滤器旁路模式中的相干交换机可以绕过窥探过滤器并且可以向所有不请求的缓存代理发出窥探请求。

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