专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07234029B2 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture 有权
标题翻译：用于减少高速缓存一致多节点架构中的存储器延迟的方法和装置
公开(公告)号：US07234029B2
公开(公告)日：2007-06-19
申请号：US09749660
申请日：2000-12-28
申请人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
发明人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0817 , G06F12/0862 , G06F2212/2542 , G06F2212/507
摘要： A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.
摘要翻译：一种用于减少多节点架构中的存储器延迟的方法。在一个实施例中，在确定高速缓存一致性协议的结果之前，向家庭节点发出推测性读请求。家庭节点启动对存储器的读取以完成推测性读取请求。高速缓存一致性协议的结果可以由相干代理确定，以在发布推测读请求之后解析高速缓存一致性。

2. 发明授权

US07996625B2 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture 有权
标题翻译：用于减少高速缓存一致多节点架构中的存储器延迟的方法和装置
公开(公告)号：US07996625B2
公开(公告)日：2011-08-09
申请号：US11790989
申请日：2007-04-30
申请人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
发明人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0817 , G06F12/0862 , G06F2212/2542 , G06F2212/507
摘要： A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.
摘要翻译：一种用于减少多节点架构中的存储器延迟的方法。在一个实施例中，在确定高速缓存一致性协议的结果之前，向家庭节点发出推测性读请求。家庭节点启动对存储器的读取以完成推测性读取请求。高速缓存一致性协议的结果可以由相干代理确定，以在发布推测读请求之后解析高速缓存一致性。

3. 发明授权

US06615319B2 Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architecture 有权
公开(公告)号：US06615319B2
公开(公告)日：2003-09-02
申请号：US09752937
申请日：2000-12-29
申请人： Manoj Khare , Lily P. Looi , Akhilesh Kumar , Faye A. Briggs
发明人： Manoj Khare , Lily P. Looi , Akhilesh Kumar , Faye A. Briggs
IPC分类号： G06F1200
CPC分类号： G06F12/0822 , G06F12/082 , G06F12/0828 , G06F12/0831 , G06F2212/507
摘要： According to one embodiment, a method is disclosed. The method comprises receiving a read request from a first node in a multi-node computer system to read data from a memory at a second node. Subsequently, a write request from a third node is received to write data to the memory at the second node. The read request and write request is detected at conflict detection circuitry. Finally, read data from the memory at the second node is transmitted to the first node.

4. 发明授权

US06810467B1 Method and apparatus for centralized snoop filtering 有权
标题翻译：用于集中侦听过滤的方法和装置
公开(公告)号：US06810467B1
公开(公告)日：2004-10-26
申请号：US09643382
申请日：2000-08-21
申请人： Manoj Khare , Faye A. Briggs , Kai Cheng , Lily Pao Looi
发明人： Manoj Khare , Faye A. Briggs , Kai Cheng , Lily Pao Looi
IPC分类号： G06F1208
CPC分类号： G06F12/0831 , G06F12/0822 , G06F12/0828 , G06F2212/507
摘要： An example embodiment of a computer system utilizing a central snoop filter includes several nodes coupled together via a switching device. Each of the nodes may include several processors and caches as well as a block of system memory. All traffic from one node to another takes place through the switching device. The switching device includes a snoop filter that tracks cache line coherency information for all caches in the computer system. The snoop filter has enough entries to track the tags and state information for all entries in all caches in all of the system's nodes. In addition to the tag and state information, the snoop filter stores information indicating which of the nodes has a copy of each cache line. The snoop filter serves in part to keep snoop transactions from being performed at nodes that do not contain a copy of the subject cache line, thereby reducing system overhead, reducing traffic across the system interconnect busses, and reducing the amount of time required to perform snoop transactions.
摘要翻译：利用中央窥探滤波器的计算机系统的示例性实施例包括经由交换设备耦合在一起的多个节点。每个节点可以包括几个处理器和高速缓存以及系统存储器块。从一个节点到另一个节点的所有业务通过交换设备进行。交换设备包括一个窥探过滤器，其跟踪计算机系统中所有高速缓存的高速缓存行一致性信息。监听过滤器具有足够的条目来跟踪所有系统节点中所有高速缓存中所有条目的标签和状态信息。除了标签和状态信息之外，窥探过滤器存储指示哪个节点具有每个高速缓存行的副本的信息。窥探过滤器部分地用于在不包含主体高速缓存行的副本的节点处执行窥探事务，从而减少系统开销，减少跨系统互连总线的流量，并减少执行窥探所需的时间量交易。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式