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11. 发明申请

US20070102738A1 LIGHT SHIELD FOR CMOS IMAGER 有权
标题翻译： CMOS成像器的光栅
公开(公告)号：US20070102738A1
公开(公告)日：2007-05-10
申请号：US11164072
申请日：2005-11-09
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe
IPC分类号： H01L31/113 , H01L31/062
CPC分类号： H01L27/14623 , H01L27/14685
摘要： The present invention provides a light shield for shielding the floating diffusion of a complementary metal-oxide semiconductor (CMOS) imager. In accordance with an embodiment of the present invention, there is provided a pixel sensor cell including: a device region formed on a substrate; and a first layer of material forming a sidewall adjacent to a side of the device region for blocking electromagnetic radiation from the device region.
摘要翻译：本发明提供一种用于屏蔽互补金属氧化物半导体（CMOS）成像器的浮动扩散的遮光罩。根据本发明的实施例，提供了一种像素传感器单元，包括：形成在基板上的器件区域; 以及形成与所述器件区域的一侧相邻的侧壁的第一材料层，用于阻挡来自所述器件区域的电磁辐射。

12. 发明申请

US20060113622A1 A DAMASCENE COPPER WIRING IMAGE SENSOR 有权
标题翻译： DAMASCENE铜接线图像传感器
公开(公告)号：US20060113622A1
公开(公告)日：2006-06-01
申请号：US10904807
申请日：2004-11-30
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Anthony Stamper
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Anthony Stamper
IPC分类号： H01L31/00
CPC分类号： H01L27/14685 , H01L21/76819 , H01L21/76834 , H01L21/76838 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14687
摘要： An image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.
摘要翻译：一种图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合更薄的层间电介质叠层，改进的厚度均匀性，以产生呈现增加的光敏度的像素阵列。在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。然后将蚀刻的开口用电介质材料重新填充。在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

13. 发明申请

US20070187787A1 PIXEL SENSOR STRUCTURE INCLUDING LIGHT PIPE AND METHOD FOR FABRICATION THEREOF 审中-公开
标题翻译：像素传感器结构包括光管及其制造方法
公开(公告)号：US20070187787A1
公开(公告)日：2007-08-16
申请号：US11276160
申请日：2006-02-16
申请人： Kristin Ackerson , James Adkisson , John Ellis-Monaghan , Jeffrey Gambino , Timothy Hoague , Mark Jaffe , Robert Leidy , Matthew Moon , Richard Passel
发明人： Kristin Ackerson , James Adkisson , John Ellis-Monaghan , Jeffrey Gambino , Timothy Hoague , Mark Jaffe , Robert Leidy , Matthew Moon , Richard Passel
IPC分类号： H01L27/14
CPC分类号： H01L27/14643 , H01L27/14625 , H01L27/14632 , H01L27/14636 , H01L27/14685 , H01L27/14687 , H01L27/14689
摘要： A pixel for an image sensor includes a photosensor located within a substrate. A patterned dielectric layer having an aperture registered with the photosensor is located over the substrate. A lens structure is located over the dielectric layer and also registered with the photosensor. A liner layer is located contiguously upon a top surface of the dielectric layer, and the sidewalls and bottom of the aperture. The liner layer provides for enhanced reflection for off-axis incoming light and enhanced capture thereof by the photosensor. When the aperture does not provide a dielectric layer border for a metallization layer embedded within the dielectric layer, an exposed edge of the metallization layer may be chamfered.
摘要翻译：用于图像传感器的像素包括位于衬底内的光电传感器。具有与光电传感器对准的孔径的图案化电介质层位于衬底上。透镜结构位于电介质层上方并且还与光电传感器配准。衬垫层连续地定位在电介质层的顶表面上，孔的侧壁和底部。衬垫层为离轴入射光提供增强的反射，并且通过光电传感器增强其捕获。当孔径不为嵌入在电介质层内的金属化层提供介电层边界时，金属化层的暴露边缘可以被倒角。

14. 发明申请

US20060226456A1 PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL AND METHOD THEREOF 有权
标题翻译：具有减少的钉扎层障碍物的像素传感器电池及其方法
公开(公告)号：US20060226456A1
公开(公告)日：2006-10-12
申请号：US10907570
申请日：2005-04-06
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
IPC分类号： H01L31/113
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

15. 发明申请

US20080073742A1 STACKED IMAGE PACKAGE 有权
标题翻译：堆叠图像包
公开(公告)号：US20080073742A1
公开(公告)日：2008-03-27
申请号：US11943277
申请日：2007-11-20
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Stephen Luce , Richard Rassell , Edmund Sprogis
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Stephen Luce , Richard Rassell , Edmund Sprogis
IPC分类号： H01L31/00 , H01L21/98
CPC分类号： H01L27/14618 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/13091 , H01L2924/15151 , H01L2924/00014 , H01L2924/00
摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.
摘要翻译：用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。互连装置提供例如与手机的空间限制相匹配的CSP。该布置还利用最小的线长度来降低噪声。将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

16. 发明申请

US20070114622A1 DAMASCENE COPPER WIRING OPTICAL IMAGE SENSOR 有权
标题翻译： DAMASCENE铜接线光学图像传感器
公开(公告)号：US20070114622A1
公开(公告)日：2007-05-24
申请号：US11623977
申请日：2007-01-17
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Anthony Stamper
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Anthony Stamper
IPC分类号： H01L29/82
CPC分类号： H01L27/14685 , H01L21/76819 , H01L21/76834 , H01L21/76838 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14687
摘要： A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a inner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.
摘要翻译： CMOS图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合具有改进的厚度均匀性的内部层间电介质叠层，以产生呈现增加的光敏度的像素阵列。在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。然后将蚀刻的开口用电介质材料重新填充。在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

17. 发明申请

US20060273397A1 PROTECT DIODES FOR HYBRID-ORIENTATION SUBSTRATE STRUCTURES 失效
标题翻译：用于混合基底结构的保护二极管
公开(公告)号：US20060273397A1
公开(公告)日：2006-12-07
申请号：US10908926
申请日：2005-06-01
申请人： James Adkisson , Jeffrey Gambino , Alain Loiseau , Kirk Peterson
发明人： James Adkisson , Jeffrey Gambino , Alain Loiseau , Kirk Peterson
IPC分类号： H01L23/62
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0255 , H01L27/0922 , H01L27/1207 , H01L29/045
摘要： A semiconductor structure and method for forming the same. The structure includes a hybrid orientation block having first and second silicon regions having different lattice orientations. The first silicon region is directly on the block, while the second silicon region is physically isolated from the block by a dielectric region. First and second transistors are formed on the first and second regions, respectively. Also, first and second doped discharge prevention structures are formed on the block wherein the first doped discharge prevention structure prevents discharge damage to the first transistor, whereas the second doped discharge prevention structure prevents discharge damage to the second transistor during a plasma process. During the normal operation of the first and second transistors, the first and second discharge prevention structures behave like dielectric regions.
摘要翻译：一种半导体结构及其形成方法。该结构包括具有不同晶格取向的第一和第二硅区的混合取向嵌段。第一硅区域直接在块上，而第二硅区域通过电介质区域与块物理隔离。第一和第二晶体管分别形成在第一和第二区域上。此外，在第一掺杂放电预防结构防止对第一晶体管的放电损坏的块上形成第一和第二掺杂放电预防结构，而第二掺杂放电预防结构在等离子体处理期间防止对第二晶体管的放电损坏。在第一和第二晶体管的正常操作期间，第一和第二放电预防结构表现得像电介质区域。

18. 发明申请

US20070293025A1 PROTECT DIODES FOR HYBRID-ORIENTATION SUBSTRATE STRUCTURES 失效
标题翻译：用于混合基底结构的保护二极管
公开(公告)号：US20070293025A1
公开(公告)日：2007-12-20
申请号：US11849489
申请日：2007-09-04
申请人： James Adkisson , Jeffrey Gambino , Alain Loiseau , Kirk Peterson
发明人： James Adkisson , Jeffrey Gambino , Alain Loiseau , Kirk Peterson
IPC分类号： H01L21/04
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0255 , H01L27/0922 , H01L27/1207 , H01L29/045
摘要： A semiconductor structure fabrication method. First, a semiconductor structure is provided including (a) a semiconductor block having a first semiconductor material doped with a first doping polarity and having a first lattice orientation, and (b) a semiconductor region on the semiconductor block, wherein the semiconductor region is physically isolated from the semiconductor block by a dielectric region, and wherein the semiconductor region includes a second semiconductor material (i) doped with a second doping polarity opposite to the first doping polarity and (ii) having a second lattice orientation different from the first lattice orientation. Next, first and second gate stacks are formed on the semiconductor block and the semiconductor region, respectively. Then, (i) first and second S/D regions are simultaneously formed in the semiconductor block on opposing sides of the first gate stack and (ii) first and second discharge prevention semiconductor regions in the semiconductor block.
摘要翻译：半导体结构制造方法。首先，提供半导体结构，其包括：（a）具有掺杂有第一掺杂极性且具有第一晶格取向的第一半导体材料的半导体块，以及（b）半导体块上的半导体区域，其中半导体区域是物理上的并且其中所述半导体区域包括掺杂有与所述第一掺杂极性相反的第二掺杂极性的第二半导体材料（i）和（ii）具有不同于所述第一晶格取向的第二晶格取向。接下来，分别在半导体块和半导体区域上形成第一和第二栅极叠层。然后，（i）第一和第二S / D区域同时形成在半导体块中的第一栅极堆叠的相对侧上，以及（ii）半导体块中的第一和第二放电预防半导体区域。

19. 发明申请

US20070013071A1 PROBING PADS IN KERF AREA FOR WAFER TESTING 失效
标题翻译：在KERF区域进行水分测试的探针垫
公开(公告)号：US20070013071A1
公开(公告)日：2007-01-18
申请号：US11160461
申请日：2005-06-24
申请人： James Adkisson , Timothy Daubenspeck , Jeffrey Gambino , Christopher Muzzy , Wolfgang Sauter
发明人： James Adkisson , Timothy Daubenspeck , Jeffrey Gambino , Christopher Muzzy , Wolfgang Sauter
IPC分类号： H01L23/52
CPC分类号： H01L24/05 , H01L22/32 , H01L22/34 , H01L24/06 , H01L2224/05624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/14 , H01L2924/00014
摘要： A structure and a method for forming the same. The structure includes (a) a substrate having a top substrate surface; (b) an integrated circuit on the top substrate surface, wherein the integrated circuit includes a bond pad electrically connected to a transistor of the integrated circuit; (c) a protection ring on the top substrate surface and on a perimeter of the integrated circuit; (c) a kerf region on the top substrate surface, wherein the protection ring is sandwiched between and physically isolates the integrated circuit and the kerf region, wherein the kerf region includes a probe pad electrically connected to the bond pad, and wherein the kerf region is adapted to be destroyed by chip dicing without damaging the integrated circuit and the protection ring.
摘要翻译：一种结构及其形成方法。该结构包括（a）具有顶部衬底表面的衬底; （b）在顶部衬底表面上的集成电路，其中所述集成电路包括电连接到所述集成电路的晶体管的接合焊盘; （c）在顶部基板表面上和集成电路的周边上的保护环; （c）顶部衬底表面上的切口区域，其中所述保护环夹在所述集成电路和所述切口区域之间并物理隔离所述集成电路和所述切口区域，其中所述切口区域包括电连接到所述接合焊盘的探针焊盘，并且其中所述切口区域适用于通过芯片切割而损坏，而不会损坏集成电路和保护环。

20. 发明申请

US20070296006A1 STRUCTURE FOR PIXEL SENSOR CELL THAT COLLECTS ELECTRONS AND HOLES 失效
标题翻译：用于收集电子和孔的像素传感器单元的结构
公开(公告)号：US20070296006A1
公开(公告)日：2007-12-27
申请号：US11850776
申请日：2007-09-06
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
IPC分类号： H01L31/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14689 , H01L31/035281 , H01L31/1037
摘要： The present invention relates to a design structure for a pixel sensor cell. The pixel sensor cell approximately doubles the available signal for a given quanta of light. A design structure for a pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.
摘要翻译：本发明涉及一种像素传感器单元的设计结构。像素传感器单元对于给定的光量大约使可用信号加倍。具有降低的复杂度的像素传感器单元的设计结构包括形成在基板的表面下面的n型收集阱区域，用于收集电子辐射产生的电子撞击在像素传感器单元上，以及p型收集阱区域用于收集由撞击光子产生的孔的基板的表面。具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小的第一输入和第二输入的信号。

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