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11. 发明授权

US08862944B2 Isolation of faulty links in a transmission medium 有权
标题翻译：隔离传输介质中的故障链路
公开(公告)号：US08862944B2
公开(公告)日：2014-10-14
申请号：US12822508
申请日：2010-06-24
申请人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright , Lisa C. Gower
发明人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
IPC分类号： G06F11/00 , G06F11/20 , G06F11/10 , H04L1/00
CPC分类号： G06F11/10 , G06F11/2005 , H04L1/0061 , H04L2001/0096
摘要： Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links. An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
摘要翻译：隔离传输介质中的故障链路，包括包括通过具有多个传输链路的多链路传输介质接收原子数据单元的方法。检测到错误状况，并且确定错误状况被隔离到单个传输链路。在由定时器指定的间隔内，确定单个传输链路是否已经被隔离为先前被隔离的传输链路指定的次数。如果单个传输链路在由定时器指定的间隔内已经被隔离为失败的传输链路指定的次数，则：将单个传输链路识别为有故障的传输链路; 重置定时器; 并输出单个传输链路的标识符。

12. 发明申请

US20110320881A1 ISOLATION OF FAULTY LINKS IN A TRANSMISSION MEDIUM 有权
标题翻译：在传输介质中分离故障链路
公开(公告)号：US20110320881A1
公开(公告)日：2011-12-29
申请号：US12822508
申请日：2010-06-24
申请人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
发明人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
IPC分类号： G06F11/34
CPC分类号： G06F11/10 , G06F11/2005 , H04L1/0061 , H04L2001/0096
摘要： Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
摘要翻译：隔离传输介质中的故障链路，包括包括通过具有多个传输链路的多链路传输介质接收原子数据单元的方法检测到错误状况，并且确定错误状况被隔离为单个传输链路。在由定时器指定的间隔内，确定单个传输链路是否已经被隔离为先前被隔离的传输链路指定的次数。如果单个传输链路在由定时器指定的间隔内已经被隔离为失败的传输链路指定的次数，则：将单个传输链路识别为有故障的传输链路; 重置定时器; 并输出单个传输链路的标识符。

13. 发明授权

US08697567B2 Implementing decoupling devices inside a TSV DRAM stack 失效
标题翻译：在TSV DRAM堆栈内实现去耦器件
公开(公告)号：US08697567B2
公开(公告)日：2014-04-15
申请号：US13477371
申请日：2012-05-22
申请人： Joab D. Henderson , Kyu-hyoun Kim , Warren E. Maule , Kenneth L. Wright
发明人： Joab D. Henderson , Kyu-hyoun Kim , Warren E. Maule , Kenneth L. Wright
IPC分类号： H01L21/768
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/498 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L2224/0401 , H01L2224/05009 , H01L2224/05027 , H01L2224/13014 , H01L2224/13021 , H01L2224/13025 , H01L2224/131 , H01L2224/14051 , H01L2224/1411 , H01L2224/1613 , H01L2224/16146 , H01L2224/17106 , H01L2224/73204 , H01L2225/06513 , H01L2225/06541 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
摘要： A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled with a conducting material. A layer of glass is grown on both the top and bottom of the DRAM providing an insulator. A layer of metal is grown on each glass layer providing a conductor. The metal and glass layers are etched through to TSVs with a gap provided around the perimeter of via pads. A respective solder ball is formed on the TSVs to connect to another DRAM chip in the DRAM TSV stack. The metal layers are connected to at least one TSV by one respective solder ball and are connected to a voltage source and a dielectric is inserted between the metal layers in the DRAM TSV stack to complete the decoupling capacitor.
摘要翻译：提供了一种用于在DRAM TSV堆栈内实现去耦电容器的方法和结构。形成有多个完全延伸穿过衬底并填充有导电材料的TSV的DRAM。在提供绝缘体的DRAM的顶部和底部都生长玻璃层。在提供导体的每个玻璃层上生长一层金属。金属和玻璃层被蚀刻到具有围绕通孔焊盘的周边设置的间隙的TSV。在TSV上形成相应的焊球以连接到DRAM TSV堆叠中的另一个DRAM芯片。金属层通过一个相应的焊球连接到至少一个TSV，并且连接到电压源，并且电介质插入在DRAM TSV堆叠中的金属层之间以完成去耦电容器。

14. 发明申请

US20090251988A1 SYSTEM AND METHOD FOR PROVIDING A NON-POWER-OF-TWO BURST LENGTH IN A MEMORY SYSTEM 有权
标题翻译：用于在存储器系统中提供非功率的两个BURST长度的系统和方法
公开(公告)号：US20090251988A1
公开(公告)日：2009-10-08
申请号：US12061045
申请日：2008-04-02
申请人： Kyu-hyoun Kim , Paul W. Coteus , Warren E. Maule , Kenneth L. Wright
发明人： Kyu-hyoun Kim , Paul W. Coteus , Warren E. Maule , Kenneth L. Wright
IPC分类号： G11C8/00
CPC分类号： G11C5/00 , G11C7/1018
摘要： A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.
摘要翻译：提供了一种用于非二次突发长度的存储器系统，存储器接口装置和方法。存储器系统包括具有非二次突发长度逻辑的多个存储器件和包括非二次突发长度生成逻辑的存储器接口器件。非功率二突发长度生成逻辑从两个功率值扩展突发长度，以将错误检测码插入到存储器接口设备和多个存储器件之间的数据线上的突发中。

15. 发明申请

US20130313705A1 IMPLEMENTING DECOUPLING DEVICES INSIDE A TSV DRAM STACK 失效
标题翻译：在TSV DRAM堆栈中实现解码器件
公开(公告)号：US20130313705A1
公开(公告)日：2013-11-28
申请号：US13477371
申请日：2012-05-22
申请人： Joab D. Henderson , Kyu-hyoun Kim , Warren E. Maule , Kenneth L. Wright
发明人： Joab D. Henderson , Kyu-hyoun Kim , Warren E. Maule , Kenneth L. Wright
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/498 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L2224/0401 , H01L2224/05009 , H01L2224/05027 , H01L2224/13014 , H01L2224/13021 , H01L2224/13025 , H01L2224/131 , H01L2224/14051 , H01L2224/1411 , H01L2224/1613 , H01L2224/16146 , H01L2224/17106 , H01L2224/73204 , H01L2225/06513 , H01L2225/06541 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
摘要： A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled with a conducting material. A layer of glass is grown on both the top and bottom of the DRAM providing an insulator. A layer of metal is grown on each glass layer providing a conductor. The metal and glass layers are etched through to TSVs with a gap provided around the perimeter of via pads. A respective solder ball is formed on the TSVs to connect to another DRAM chip in the DRAM TSV stack. The metal layers are connected to at least one TSV by one respective solder ball and are connected to a voltage source and a dielectric is inserted between the metal layers in the DRAM TSV stack to complete the decoupling capacitor.
摘要翻译：提供了一种用于在DRAM TSV堆栈内实现去耦电容器的方法和结构。形成有多个完全延伸穿过衬底并填充有导电材料的TSV的DRAM。在提供绝缘体的DRAM的顶部和底部都生长玻璃层。在提供导体的每个玻璃层上生长一层金属。金属和玻璃层被蚀刻到具有围绕通孔焊盘的周边设置的间隙的TSV。在TSV上形成相应的焊球以连接到DRAM TSV堆叠中的另一个DRAM芯片。金属层通过一个相应的焊球连接到至少一个TSV，并且连接到电压源，并且电介质插入在DRAM TSV堆叠中的金属层之间以完成去耦电容器。

16. 发明授权

US08023358B2 System and method for providing a non-power-of-two burst length in a memory system 有权
标题翻译：在存储器系统中提供非二次突发长度的系统和方法
公开(公告)号：US08023358B2
公开(公告)日：2011-09-20
申请号：US12061045
申请日：2008-04-02
申请人： Kyu-hyoun Kim , Paul W. Coteus , Warren E. Maule , Kenneth L. Wright
发明人： Kyu-hyoun Kim , Paul W. Coteus , Warren E. Maule , Kenneth L. Wright
IPC分类号： G11C8/00
CPC分类号： G11C5/00 , G11C7/1018
摘要： A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.
摘要翻译：提供了一种用于非二次突发长度的存储器系统，存储器接口装置和方法。存储器系统包括具有非二次突发长度逻辑的多个存储器件和包括非二次突发长度生成逻辑的存储器接口器件。非功率二突发长度生成逻辑从两个功率值扩展突发长度，以将错误检测码插入到存储器接口设备和多个存储器件之间的数据线上的突发中。

17. 发明申请

US20110029807A1 IMPLEMENTING ENHANCED MEMORY RELIABILITY USING MEMORY SCRUB OPERATIONS 有权
标题翻译：使用存储器SCRUB操作实现增强的存储器可靠性
公开(公告)号：US20110029807A1
公开(公告)日：2011-02-03
申请号：US12510311
申请日：2009-07-28
申请人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
发明人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
IPC分类号： G11C29/08 , G06F11/14 , G06F11/26
CPC分类号： G06F11/106
摘要： A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.
摘要翻译：一种用于使用存储器擦除操作来实现增强的存储器可靠性以确定间歇可校正错误的频率的方法和电路，以及提供了所述主题电路所在的设计结构。间歇性的内存擦除在移动到下一个内存擦除地址之前执行至少两次读取。跟踪识别出间歇性错误的多个间歇性错误，响应于识别一个失败的读取和一次读取至少两个读取。

18. 发明申请

US20130151867A1 SYNCHRONIZED COMMAND THROTTLING FOR MULTI-CHANNEL DUTY-CYCLE BASED MEMORY POWER MANAGEMENT 失效
标题翻译：基于多通道占空比的存储器电源管理的同步指令脉宽调制
公开(公告)号：US20130151867A1
公开(公告)日：2013-06-13
申请号：US13314379
申请日：2011-12-08
申请人： John S. Dodson , Karthick Rajamani , Eric E. Retter , Kenneth L. Wright
发明人： John S. Dodson , Karthick Rajamani , Eric E. Retter , Kenneth L. Wright
IPC分类号： G06F1/26 , G06F12/00
CPC分类号： G06F3/0644 , G06F1/32 , G06F1/3206 , G06F1/3275 , G06F13/16 , G11C5/147 , G11C11/4074 , Y02D10/14
摘要： A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., a synchronization bit or bits) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted. Each of the multiple memory controllers with the asserted associated synchronization indication then transmits the forwarded synchronization command to associated power control logic.
摘要翻译：在分区存储器子系统中用于存储器命令调节的技术包括由包含在多个存储器控制器中的主存储器控制器接受同步命令。同步命令包括命令数据，其包括用于多个存储器控制器中的每一个的相关联的同步指示（例如，同步位或位），并且多个存储器控制器中的每一个控制分区存储器子系统的相应分区。响应于接收到同步命令，主存储器控制器将同步命令转发到多个存储器控制器。响应于接收到转发的同步命令，多个存储器控制器中的每个存储器控制器断言相关联的状态位。响应于接收到转发的同步命令，多个存储器控制器中的每一个确定相关联的同步指示是否被断言。具有断言的相关同步指示的多个存储器控制器中的每一个然后将转发的同步命令发送到相关联的功率控制逻辑。

19. 发明授权

US08103900B2 Implementing enhanced memory reliability using memory scrub operations 有权
标题翻译：使用内存清理操作实现增强的内存可靠性
公开(公告)号：US08103900B2
公开(公告)日：2012-01-24
申请号：US12510311
申请日：2009-07-28
申请人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
发明人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
IPC分类号： G06F11/00
CPC分类号： G06F11/106
摘要： A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.
摘要翻译：一种用于使用存储器擦除操作来实现增强的存储器可靠性以确定间歇可校正错误的频率的方法和电路，以及提供了所述主题电路所在的设计结构。间歇性的内存擦除在移动到下一个内存擦除地址之前执行至少两次读取。跟踪识别出间歇性错误的多个间歇性错误，响应于识别一个失败的读取和一次读取至少两个读取。

20. 发明授权

US08775906B2 Efficient storage of meta-bits within a system memory 失效
公开(公告)号：US08775906B2
公开(公告)日：2014-07-08
申请号：US13611909
申请日：2012-09-12
申请人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
发明人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
IPC分类号： G11C29/42 , G06F11/10 , G11C29/54 , G11C29/04
CPC分类号： G06F11/1076 , G06F11/1064 , G06F12/0815 , G06F12/0895 , G11C2029/0411
摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

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