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1. 发明申请

US20110320881A1 ISOLATION OF FAULTY LINKS IN A TRANSMISSION MEDIUM 有权
标题翻译：在传输介质中分离故障链路
公开(公告)号：US20110320881A1
公开(公告)日：2011-12-29
申请号：US12822508
申请日：2010-06-24
申请人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
发明人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
IPC分类号： G06F11/34
CPC分类号： G06F11/10 , G06F11/2005 , H04L1/0061 , H04L2001/0096
摘要： Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
摘要翻译：隔离传输介质中的故障链路，包括包括通过具有多个传输链路的多链路传输介质接收原子数据单元的方法检测到错误状况，并且确定错误状况被隔离为单个传输链路。在由定时器指定的间隔内，确定单个传输链路是否已经被隔离为先前被隔离的传输链路指定的次数。如果单个传输链路在由定时器指定的间隔内已经被隔离为失败的传输链路指定的次数，则：将单个传输链路识别为有故障的传输链路; 重置定时器; 并输出单个传输链路的标识符。

2. 发明授权

US08862944B2 Isolation of faulty links in a transmission medium 有权
标题翻译：隔离传输介质中的故障链路
公开(公告)号：US08862944B2
公开(公告)日：2014-10-14
申请号：US12822508
申请日：2010-06-24
申请人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright , Lisa C. Gower
发明人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
IPC分类号： G06F11/00 , G06F11/20 , G06F11/10 , H04L1/00
CPC分类号： G06F11/10 , G06F11/2005 , H04L1/0061 , H04L2001/0096
摘要： Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links. An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
摘要翻译：隔离传输介质中的故障链路，包括包括通过具有多个传输链路的多链路传输介质接收原子数据单元的方法。检测到错误状况，并且确定错误状况被隔离到单个传输链路。在由定时器指定的间隔内，确定单个传输链路是否已经被隔离为先前被隔离的传输链路指定的次数。如果单个传输链路在由定时器指定的间隔内已经被隔离为失败的传输链路指定的次数，则：将单个传输链路识别为有故障的传输链路; 重置定时器; 并输出单个传输链路的标识符。

3. 发明申请

US20130151790A1 Efficient Storage of Meta-Bits Within a System Memory 失效
公开(公告)号：US20130151790A1
公开(公告)日：2013-06-13
申请号：US13611909
申请日：2012-09-12
申请人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
发明人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
IPC分类号： G06F12/08
CPC分类号： G06F11/1076 , G06F11/1064 , G06F12/0815 , G06F12/0895 , G11C2029/0411
摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

4. 发明申请

US20130151867A1 SYNCHRONIZED COMMAND THROTTLING FOR MULTI-CHANNEL DUTY-CYCLE BASED MEMORY POWER MANAGEMENT 失效
标题翻译：基于多通道占空比的存储器电源管理的同步指令脉宽调制
公开(公告)号：US20130151867A1
公开(公告)日：2013-06-13
申请号：US13314379
申请日：2011-12-08
申请人： John S. Dodson , Karthick Rajamani , Eric E. Retter , Kenneth L. Wright
发明人： John S. Dodson , Karthick Rajamani , Eric E. Retter , Kenneth L. Wright
IPC分类号： G06F1/26 , G06F12/00
CPC分类号： G06F3/0644 , G06F1/32 , G06F1/3206 , G06F1/3275 , G06F13/16 , G11C5/147 , G11C11/4074 , Y02D10/14
摘要： A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., a synchronization bit or bits) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted. Each of the multiple memory controllers with the asserted associated synchronization indication then transmits the forwarded synchronization command to associated power control logic.
摘要翻译：在分区存储器子系统中用于存储器命令调节的技术包括由包含在多个存储器控制器中的主存储器控制器接受同步命令。同步命令包括命令数据，其包括用于多个存储器控制器中的每一个的相关联的同步指示（例如，同步位或位），并且多个存储器控制器中的每一个控制分区存储器子系统的相应分区。响应于接收到同步命令，主存储器控制器将同步命令转发到多个存储器控制器。响应于接收到转发的同步命令，多个存储器控制器中的每个存储器控制器断言相关联的状态位。响应于接收到转发的同步命令，多个存储器控制器中的每一个确定相关联的同步指示是否被断言。具有断言的相关同步指示的多个存储器控制器中的每一个然后将转发的同步命令发送到相关联的功率控制逻辑。

5. 发明授权

US08775906B2 Efficient storage of meta-bits within a system memory 失效
公开(公告)号：US08775906B2
公开(公告)日：2014-07-08
申请号：US13611909
申请日：2012-09-12
申请人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
发明人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
IPC分类号： G11C29/42 , G06F11/10 , G11C29/54 , G11C29/04
CPC分类号： G06F11/1076 , G06F11/1064 , G06F12/0815 , G06F12/0895 , G11C2029/0411
摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

6. 发明申请

US20130151929A1 Efficient Storage of Meta-Bits Within a System Memory 有权
标题翻译：系统内存中元位的高效存储
公开(公告)号：US20130151929A1
公开(公告)日：2013-06-13
申请号：US13313364
申请日：2011-12-07
申请人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
发明人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
IPC分类号： G06F11/16 , G06F12/08
CPC分类号： G06F11/1076 , G06F11/1064 , G06F12/0815 , G06F12/0895 , G11C2029/0411
摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.
摘要翻译：提供了用于在系统存储器内有效存储元位的机制。这些机制将L / G位和SUE位组合以形成元位。机制然后在第一个数据周期上确定高速缓存行的本地/全局状态。这些机制将数据转发到请求的高速缓存，并且请求高速缓存可以基于高速缓存行的本地/全局状态全局重新发出请求。这些机制然后在数据的第二个或随后的周期中确定高速缓存行的特殊的不可校正错误状态。机制执行错误处理，而不管请求是否在全球重新发布。

7. 发明授权

US08775904B2 Efficient storage of meta-bits within a system memory 有权
标题翻译：元位在系统存储器内的高效存储
公开(公告)号：US08775904B2
公开(公告)日：2014-07-08
申请号：US13313364
申请日：2011-12-07
申请人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
发明人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
IPC分类号： G11C29/42 , G06F11/10 , G11C29/54 , G11C29/04
CPC分类号： G06F11/1076 , G06F11/1064 , G06F12/0815 , G06F12/0895 , G11C2029/0411
摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.
摘要翻译：提供了用于在系统存储器内有效存储元位的机制。这些机制将L / G位和SUE位组合以形成元位。机制然后在第一个数据周期上确定高速缓存行的本地/全局状态。这些机制将数据转发到请求的高速缓存，并且请求高速缓存可以基于高速缓存行的本地/全局状态全局重新发出请求。这些机制然后在数据的第二个或随后的周期中确定高速缓存行的特殊的不可校正错误状态。机制执行错误处理，而不管请求是否在全球重新发布。

8. 发明授权

US4529305A Examining a gemstone 失效
标题翻译：检查宝石
公开(公告)号：US4529305A
公开(公告)日：1985-07-16
申请号：US395245
申请日：1982-07-06
申请人： Walter T. Welford , Andrew D. G. Stewart , John S. Dodson
发明人： Walter T. Welford , Andrew D. G. Stewart , John S. Dodson
IPC分类号： G01N21/87
CPC分类号： G01N21/87
摘要： Method and apparatus for examining a gemstone to determine a parameter thereof. A thin beam of light is projected onto the stone, the beam is moved relative to the stone, the position where the beam strikes the stone is sensed in a direction different from that in which the beam is projected, and a parameter is determined making use of information derived from such sensing.
摘要翻译：用于检查宝石以确定其参数的方法和装置。光束投射到石头上，光束相对于石头移动，光束撞击石头的位置在与投影光束不同的方向上被感测，并且确定使用参数从这种感知得到的信息。

9. 发明申请

US20130212330A1 MEMORY RECORDER QUEUE BIASING PRECEDING HIGH LATENCY OPERATIONS 有权
标题翻译：内存记录器排队高效率运行
公开(公告)号：US20130212330A1
公开(公告)日：2013-08-15
申请号：US13371906
申请日：2012-02-13
申请人： Mark A. Brittain , John S. Dodson , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Mark A. Brittain , John S. Dodson , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00
CPC分类号： G11C11/40607 , G06F13/1626 , G06F13/1689
摘要： A memory system and data processing system for controlling memory refresh operations in dynamic random access memories. The memory controller comprises logic that: tracks a time remaining before a scheduled time for performing a high priority, high latency operation a first memory rank of the memory system; responsive to the time remaining reaching a pre-established early notification time before the schedule time for performing the high priority, high latency operation, biases the re-order queue containing memory access operations targeting the plurality of ranks to prioritize scheduling of any first memory access operations that target the first memory rank. The logic further: schedules the first memory access operations to the first memory rank for early completion relative to other memory access operations in the re-order queue that target other memory ranks; and performs the high priority, high latency operation at the first memory rank at the scheduled time.
摘要翻译：一种用于控制动态随机存取存储器中的存储器刷新操作的存储器系统和数据处理系统。存储器控制器包括以下逻辑：跟踪在用于执行高优先级高等待时间操作的预定时间之前的剩余时间存储器系统的第一存储器等级; 响应于在执行高优先级高等待时间操作的调度时间之前达到预先建立的早期通知时间的时间，偏置包含针对多个等级的存储器访问操作的重新排序队列，以优先排序任何第一存储器访问针对第一个内存排名的操作。该逻辑进一步：将第一存储器访问操作调度到第一存储器等级以便相对于针对其他存储器排序的重新排序队列中的其他存储器访问操作来提前完成; 并且在预定时间在第一存储器等级执行高优先级，高延迟操作。

10. 发明授权

US08489807B2 Techniques for performing refresh operations in high-density memories 失效
标题翻译：在高密度存储器中执行刷新操作的技术
公开(公告)号：US08489807B2
公开(公告)日：2013-07-16
申请号：US12959637
申请日：2010-12-03
申请人： John S. Dodson , Benjiman L. Goodman , Hillery C. Hunter , Stephen Powell , Jeffrey A. Stuecheli
发明人： John S. Dodson , Benjiman L. Goodman , Hillery C. Hunter , Stephen Powell , Jeffrey A. Stuecheli
IPC分类号： G06F12/00
CPC分类号： G11C11/40603
摘要： Techniques for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value, a refresh operation is performed as soon as possible. In a determination that the refresh backlog count is not greater than the first predetermined value, a refresh operation is performed after a delay of an idle count value.
摘要翻译：公开了用于执行刷新操作的技术。响应于存储器操作的完成，确定刷新积压计数是否大于第一预定值。在确定刷新积压计数大于第一预定值的情况下，尽可能快地执行刷新操作。在确定刷新积压计数不大于第一预定值的情况下，在空闲计数值的延迟之后执行刷新操作。

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