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11. 发明申请

US20050001265A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050001265A1
公开(公告)日：2005-01-06
申请号：US10864518
申请日：2004-06-10
申请人： Satoshi Shiraki , Yoshiaki Nakayama , Shoji Mizuno , Takashi Nakano , Akira Yamada
发明人： Satoshi Shiraki , Yoshiaki Nakayama , Shoji Mizuno , Takashi Nakano , Akira Yamada
IPC分类号： H01L21/76 , H01L21/336 , H01L21/763 , H01L21/8234 , H01L27/08 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/786 , H01L29/76
CPC分类号： H01L29/7824 , H01L21/26586 , H01L21/76286 , H01L21/763 , H01L21/823418 , H01L21/823456 , H01L21/823462 , H01L21/823481 , H01L29/0696 , H01L29/1041 , H01L29/105 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66681 , H01L29/66795 , H01L29/7825 , H01L29/7831 , H01L29/7835
摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.
摘要翻译：半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

12. 发明授权

US06279585B1 Etching method and method for manufacturing semiconductor device using the same 有权
标题翻译：使用其制造半导体器件的蚀刻方法和方法
公开(公告)号：US06279585B1
公开(公告)日：2001-08-28
申请号：US09390679
申请日：1999-09-07
申请人： Satoshi Shiraki , Makoto Ohkawa
发明人： Satoshi Shiraki , Makoto Ohkawa
IPC分类号： H01L21302
CPC分类号： H01L27/1203 , H01L21/3211 , H01L21/32134 , H01L21/84
摘要： In a method for manufacturing a semiconductor device, a barrier metal disposed on a metallic thin film for forming a thin film resistor is patterned by wet-etching. The wet-etching produces a residue of the barrier metal. The residue is removed after the oxidation thereof. Accordingly the residue is completely removed. As a result, the patterning of the thin film resistor is stably performed, and short-circuit does not occur to a wiring pattern disposed above the barrier metal.
摘要翻译：在制造半导体器件的方法中，通过湿法刻蚀图案化设置在用于形成薄膜电阻器的金属薄膜上的阻挡金属。湿蚀刻产生阻挡金属的残留物。残余物在氧化后除去。因此残留物被完全除去。结果，稳定地执行薄膜电阻器的图案化，并且在布置在阻挡金属之上的布线图案上不会发生短路。

13. 发明授权

US09240445B2 Lateral semiconductor device 有权
标题翻译：侧面半导体器件
公开(公告)号：US09240445B2
公开(公告)日：2016-01-19
申请号：US14113419
申请日：2012-05-10
申请人： Takashi Suzuki , Norihito Tokura , Satoshi Shiraki , Shigeki Takahashi , Youichi Ashida , Akira Yamada
发明人： Takashi Suzuki , Norihito Tokura , Satoshi Shiraki , Shigeki Takahashi , Youichi Ashida , Akira Yamada
IPC分类号： H01L23/62 , H01L29/06 , H01L29/40 , H01L29/861
CPC分类号： H01L29/063 , H01L29/0692 , H01L29/402 , H01L29/404 , H01L29/405 , H01L29/861
摘要： A lateral semiconductor device includes a semiconductor layer, an insulating layer, and a resistive field plate. The semiconductor layer includes a first semiconductor region and a second semiconductor region at a surface portion, and the second semiconductor region makes a circuit around the first semiconductor region. The insulating layer is formed on a surface of the semiconductor layer and is disposed between the first and second semiconductor regions. The resistive field plate is formed on a surface of the insulating layer. Between the first and second semiconductor regions, a first section and a second section are adjacent to each other along a circumferential direction around the first semiconductor region. The resistive field plate includes first and second resistive field plate sections respectively formed in the first and second sections, and the first and second resistive field plate sections are separated from each other.
摘要翻译：横向半导体器件包括半导体层，绝缘层和电阻场板。半导体层包括在表面部分处的第一半导体区域和第二半导体区域，并且第二半导体区域在第一半导体区域周围形成电路。绝缘层形成在半导体层的表面上并且设置在第一和第二半导体区之间。电阻场板形成在绝缘层的表面上。在第一和第二半导体区域之间，第一部分和第二部分沿着围绕第一半导体区域的圆周方向彼此相邻。电阻场板包括分别形成在第一和第二部分中的第一和第二电阻场板部分，并且第一和第二电阻场板部分彼此分离。

14. 发明申请

US20090152668A1 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US20090152668A1
公开(公告)日：2009-06-18
申请号：US12314518
申请日：2008-12-11
申请人： Hiroki Sone , Akira Yamada , Satoshi Shiraki , Nozomu Akagi
发明人： Hiroki Sone , Akira Yamada , Satoshi Shiraki , Nozomu Akagi
IPC分类号： H01L25/16 , H01L23/495
CPC分类号： H01L27/1203 , H01L23/49589 , H01L23/585 , H01L24/48 , H01L27/092 , H01L2224/48095 , H01L2224/48247 , H01L2924/00014 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor apparatus is disclosed. The semiconductor apparatus includes an SOI substrate including an active layer, a buried insulation film and a support substrate; a low potential reference circuit part located in the active layer and operable at a first reference potential; a high potential reference circuit part located in the active layer and operable at a second reference potential; a level-shifting element forming part located in the active layer and for providing a level-shift between the first and second reference potentials; and an insulation member insulating first and second portions of the support substrate from each other, wherein locations of the first and second portions respectively correspond to the low and high potential reference circuit parts.
摘要翻译：公开了一种半导体装置。半导体装置包括：SOI基板，包括有源层，掩埋绝缘膜和支撑基板; 位于所述有源层中并且可在第一参考电位下操作的低电位参考电路部分; 位于所述有源层中并且可在第二参考电位下操作的高电位参考电路部分; 位于有源层中的电平移动元件形成部分，用于在第一和第二参考电位之间提供电平移位; 以及绝缘构件，其将所述支撑基板的第一和第二部分彼此绝缘，其中所述第一和第二部分的位置分别对应于所述低电位和高电位参考电路部分。

15. 发明授权

US06274452B1 Semiconductor device having multilayer interconnection structure and method for manufacturing the same 失效
标题翻译：具有多层互连结构的半导体装置及其制造方法
公开(公告)号：US06274452B1
公开(公告)日：2001-08-14
申请号：US08965030
申请日：1997-11-05
申请人： Shoji Miura , Satoshi Shiraki , Hajime Soga
发明人： Shoji Miura , Satoshi Shiraki , Hajime Soga
IPC分类号： H01L2120
CPC分类号： H01L28/20 , H01L21/84 , H01L27/13 , H01L2924/0002 , H01L2924/00
摘要： After an insulating layer made of BPSG is formed on a diffusion layer, a contact hole is formed to expose the diffusion layer. Then, a first aluminum layer is formed in the contact hole. Then, first and second TEOS layers are formed. Thereafter, a thin film resistor is formed on the second TEOS layer by photo-lithography and etching treatments. In this process, the other parts are covered with the second TEOS layer to prevent being damaged. As a result, occurrence of a leak current at the diffusion layer and the like can be prevented. Further, a third TEOS layer is formed on the thin film resistor, and then a second aluminum layer is formed to be electrically connected to the thin film resistor through a contact hole by an ECR dry etching treatment. In this etching treatment, the thin film resistor is not damaged due to the third TEOS layer.
摘要翻译：在扩散层上形成由BPSG制成的绝缘层之后，形成接触孔以露出扩散层。然后，在接触孔中形成第一铝层。然后，形成第一和第二TEOS层。此后，通过光刻和蚀刻处理在第二TEOS层上形成薄膜电阻器。在此过程中，其他部分被第二个TEOS层覆盖，以防止损坏。结果，可以防止在扩散层等处发生泄漏电流。此外，在薄膜电阻器上形成第三TEOS层，然后通过ECR干蚀刻处理通过接触孔形成第二铝层与薄膜电阻器电连接。在这种蚀刻处理中，由于第三TEOS层，薄膜电阻器不会被损坏。

16. 发明申请

US20120139079A1 DIODE 有权
标题翻译：二极管
公开(公告)号：US20120139079A1
公开(公告)日：2012-06-07
申请号：US13296832
申请日：2011-11-15
申请人： Norihito TOKURA , Satoshi Shiraki , Shigeki Takahashi , Shinya Sakurai , Takashi Suzuki
发明人： Norihito TOKURA , Satoshi Shiraki , Shigeki Takahashi , Shinya Sakurai , Takashi Suzuki
IPC分类号： H01L29/47
CPC分类号： H01L21/76283 , H01L27/0814 , H01L27/1203 , H01L29/0619 , H01L29/0649 , H01L29/08 , H01L29/405 , H01L29/8611
摘要： A diode has a semiconductor layer and cathode and anode electrodes on a surface of the semiconductor layer. The semiconductor layer has cathode and anode regions respectively contacting the cathode and anode electrodes. The anode region has a first diffusion region having high surface concentration, a second diffusion region having intermediate surface concentration, and a third diffusion region having low surface concentration. The first diffusion region is covered with the second and third diffusion regions. The second diffusion region has a first side surface facing the cathode region, a second side surface opposite to the cathode region, and a bottom surface extending between the first and second side surfaces. The third diffusion region covers at least one of the first corner part connecting the first side surface with the bottom surface and the second corner part connecting the second side surface with the bottom surface.
摘要翻译：二极管在半导体层的表面上具有半导体层和阴极和阳极电极。半导体层具有分别与阴极和阳极电极接触的阴极和阳极区域。阳极区域具有表面浓度高的第一扩散区域，具有中间表面浓度的第二扩散区域和具有低表面浓度的第三扩散区域。第一扩散区被第二和第三扩散区覆盖。第二扩散区域具有面对阴极区域的第一侧表面，与阴极区域相对的第二侧表面和在第一和第二侧表面之间延伸的底表面。第三扩散区域覆盖连接第一侧表面与底表面的第一角部和将第二侧表面与底表面连接的第二角部中的至少一个。

17. 发明授权

US08102047B2 Load driving device 有权
标题翻译：负载驱动装置
公开(公告)号：US08102047B2
公开(公告)日：2012-01-24
申请号：US12801187
申请日：2010-05-27
申请人： Satoshi Shiraki , Akira Yamada , Hiroyuki Ban
发明人： Satoshi Shiraki , Akira Yamada , Hiroyuki Ban
IPC分类号： H01L23/34 , H01L23/10
CPC分类号： H05K7/1432 , H01L24/73 , H01L2224/32145 , H01L2224/32245 , H01L2224/33181 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/73215 , H01L2224/73265 , H01L2924/01046 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H02M7/003 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A load driving device includes: an output power device for driving a load; a driving IC for controlling the output power device, wherein the driving IC is electrically coupled with the output power device through a wire or a connection member; and a first electrode substrate. The output power device and the driving IC are mounted on the first electrode substrate. In this case, the output power device is controlled with high speed, and a mounting area of the output power device and the driving IC is reduced.
摘要翻译：负载驱动装置包括：用于驱动负载的输出功率装置; 用于控制输出功率器件的驱动IC，其中驱动IC通过导线或连接构件与输出功率器件电耦合; 和第一电极基板。输出功率器件和驱动IC安装在第一电极基板上。在这种情况下，输出功率器件被高速控制，并且输出功率器件和驱动IC的安装面积减小。

18. 发明申请

US20110291157A1 LATERAL INSULATED GATE BIPOLAR TRANSISTOR 审中-公开
标题翻译：横向绝缘门双极晶体管
公开(公告)号：US20110291157A1
公开(公告)日：2011-12-01
申请号：US13114148
申请日：2011-05-24
申请人： Shigeki TAKAHASHI , Norihito Tokura , Satoshi Shiraki , Youichi Ashida , Akio Nakagawa
发明人： Shigeki TAKAHASHI , Norihito Tokura , Satoshi Shiraki , Youichi Ashida , Akio Nakagawa
IPC分类号： H01L29/739
CPC分类号： H01L29/7393 , H01L29/0696 , H01L29/0834 , H01L29/1095 , H01L29/405 , H01L29/7394
摘要： A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer.
摘要翻译：横向绝缘栅双极晶体管包括包括漂移层，集电极区域，沟道层，发射极区域，栅极绝缘层，栅电极，集电极，发射极和阻挡层的半导体衬底。阻挡层沿着集电极区域的两侧设置，并且位于比通道层的底部更深的深度。阻挡层的杂质浓度高于漂移层的杂质浓度。阻挡层具有靠近集电极区域的第一端和远离集电极区域的第二端。第一端位于沟道层和集电极区之间，第二端位于沟道层的底部。

19. 发明申请

US20110073904A1 Semiconductor device having SOI substrate and method for manufacturing the same 有权
标题翻译：具有SOI衬底的半导体器件及其制造方法
公开(公告)号：US20110073904A1
公开(公告)日：2011-03-31
申请号：US12923469
申请日：2010-09-23
申请人： Youichi Ashida , Norihito Tokura , Shigeki Takahashi , Yoshiaki Nakayama , Satoshi Shiraki , Kouji Senda
发明人： Youichi Ashida , Norihito Tokura , Shigeki Takahashi , Yoshiaki Nakayama , Satoshi Shiraki , Kouji Senda
IPC分类号： H01L29/739 , H01L29/06 , H01L29/78 , H01L21/762
CPC分类号： H01L27/1203 , H01L21/76264 , H01L21/84 , H01L29/0634 , H01L29/0657 , H01L29/0692 , H01L29/1608 , H01L29/404 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66128 , H01L29/7394 , H01L29/7824 , H01L29/8611
摘要： A semiconductor device includes: a SOI substrate; a semiconductor element having first and second impurity layers disposed in an active layer of the SOI substrate, the second impurity layer surrounding the first impurity layer; and multiple first and second conductive type regions disposed in a part of the active layer adjacent to an embedded insulation film of the SOI substrate. The first and second conductive type regions are alternately arranged. The first and second conductive type regions have a layout, which corresponds to the semiconductor element.
摘要翻译：半导体器件包括：SOI衬底; 半导体元件，其具有设置在所述SOI衬底的有源层中的第一和第二杂质层，所述第二杂质层围绕所述第一杂质层; 以及设置在与SOI衬底的嵌入式绝缘膜相邻的有源层的一部分中的多个第一和第二导电类型区域。交替地布置第一和第二导电类型区域。第一和第二导电类型区域具有对应于半导体元件的布局。

20. 发明授权

US07799667B2 Method for manufacturing semiconductor device with planer gate electrode and trench gate electrode 有权
标题翻译：制造具有平面栅电极和沟槽栅电极的半导体器件的方法
公开(公告)号：US07799667B2
公开(公告)日：2010-09-21
申请号：US12219008
申请日：2008-07-15
申请人： Satoshi Shiraki , Yoshiaki Nakayama , Shoji Mizuno , Takashi Nakano , Akira Yamada
发明人： Satoshi Shiraki , Yoshiaki Nakayama , Shoji Mizuno , Takashi Nakano , Akira Yamada
IPC分类号： H01L21/336
CPC分类号： H01L29/7824 , H01L21/26586 , H01L21/76286 , H01L21/763 , H01L21/823418 , H01L21/823456 , H01L21/823462 , H01L21/823481 , H01L29/0696 , H01L29/1041 , H01L29/105 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66681 , H01L29/66795 , H01L29/7825 , H01L29/7831 , H01L29/7835
摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.
摘要翻译：半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

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