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11. 发明授权

US07227255B2 Semiconductor device and method of producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07227255B2
公开(公告)日：2007-06-05
申请号：US11098501
申请日：2005-04-05
申请人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
发明人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
IPC分类号： H01L23/48
CPC分类号： H01L27/11568 , H01L21/2815 , H01L27/115 , H01L29/6656
摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
摘要翻译：一种半导体器件，其能够以近似的间隔布置字线，包括排列成阵列的多个存储晶体管，以及同时作为沿行方向延伸的同一行中的存储晶体管的栅电极的多条字线，并重复在列方向上，在多个字线之间形成绝缘膜以使字线彼此绝缘和隔离，并且字线分隔的尺寸由绝缘膜的厚度限定。

12. 发明授权

US07049180B2 Method of fabricating a memory transistor array utilizing insulated word lines as gate electrodes 失效
标题翻译：使用绝缘字线作为栅电极制造存储晶体管阵列的方法
公开(公告)号：US07049180B2
公开(公告)日：2006-05-23
申请号：US11098447
申请日：2005-04-05
申请人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
发明人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
IPC分类号： H01L21/48 , H01L29/76
CPC分类号： H01L27/11568 , H01L21/2815 , H01L27/115 , H01L29/6656
摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
摘要翻译：一种半导体器件，其能够以近似的间隔布置字线，包括排列成阵列的多个存储晶体管，以及同时作为沿行方向延伸的同一行中的存储晶体管的栅电极的多条字线，并重复在列方向上，在多个字线之间形成绝缘膜以使字线彼此绝缘和隔离，并且字线分隔的尺寸由绝缘膜的厚度限定。

13. 发明申请

US20050255652A1 Semiconductor device and method of producing the same 失效
公开(公告)号：US20050255652A1
公开(公告)日：2005-11-17
申请号：US11098447
申请日：2005-04-05
申请人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
发明人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
IPC分类号： H01L21/28 , H01L21/8246 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11568 , H01L21/2815 , H01L27/115 , H01L29/6656
摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

14. 发明授权

US06903977B2 Nonvolatile semiconductor memory device and method of producing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06903977B2
公开(公告)日：2005-06-07
申请号：US10432158
申请日：2002-09-25
申请人： Ichiro Fujiwara , Hiromi Nobukata
发明人： Ichiro Fujiwara , Hiromi Nobukata
IPC分类号： G11C16/04 , H01L21/8246 , H01L27/105 , H01L29/423 , H01L29/792 , G11C16/00
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0491 , H01L27/105 , H01L27/115 , H01L27/11573 , H01L29/42332 , H01L29/792
摘要： A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/drain regions (S, SSL, D, SBL) formed on a semiconductor substrate (SUB, W), a charge storage film (GD) having a charge storage faculty and a gate electrode (WL). Memory peripheral circuits (2a to 9) generate a first voltage (Vd) and a second voltage (Vg-Vwell), apply the first voltage (Vd) to the second source/drain region (D, SBL) by using potential (0V) of the first source/drain region (S, SSL) as reference, apply the second voltage (Vg-Vwell) to the gate electrode (WL), generate hot electrons (HE) by ionization collision on the second source/drain region (D, SBL) side, and inject the hot electrons (HE) to the charge storage film (GD) from the second source/drain region (D, SBL) side at the time of writing data.
摘要翻译：提供了适用于电荷注入效率高的逻辑结合的非易失性半导体存储器件，并且可以以低电压有效地注入热电子（HE）。存储晶体管（M）包括形成在半导体衬底（SUB，W）上的第一和第二源/漏区（S，SSL，D，SBL），具有电荷存储层的电荷存储膜（GD）（WL）。存储器外围电路（2 a至9）产生第一电压（Vd）和第二电压（Vg-Vwell），通过使用电位（0V）将第一电压（Vd）施加到第二源/漏区（D，SBL））作为参考，将第二电压（Vg-Vwell）施加到栅电极（WL），通过在第二源极/漏极区域上的电离碰撞产生热电子（HE） D，SBL）侧，并且在写入数据时从第二源/漏区（D，SBL）侧将热电子（HE）注入到电荷存储膜（GD）。

15. 发明授权

US06891262B2 Semiconductor device and method of producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06891262B2
公开(公告)日：2005-05-10
申请号：US10196636
申请日：2002-07-17
申请人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
发明人： Kazumasa Nomoto , Toshio Kobayashi , Akihiro Nakamura , Ichiro Fujiwara , Toshio Terano
IPC分类号： H01L21/28 , H01L21/8246 , H01L27/115 , H01L23/48 , H01L23/04 , H01L23/495 , H01L29/788
CPC分类号： H01L27/11568 , H01L21/2815 , H01L27/115 , H01L29/6656
摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.
摘要翻译：一种半导体器件，其能够以近似的间隔布置字线，包括排列成阵列的多个存储晶体管，以及同时作为沿行方向延伸的同一行中的存储晶体管的栅电极的多条字线，并重复在列方向上，在多个字线之间形成绝缘膜，以使字线彼此绝缘和隔离，并且字线分隔的尺寸由绝缘膜的厚度限定。

16. 发明授权

US5777977A Recording and reproducing apparatus 失效
标题翻译：记录和再现设备
公开(公告)号：US5777977A
公开(公告)日：1998-07-07
申请号：US701687
申请日：1996-08-22
申请人： Ichiro Fujiwara , Akio Machida , Shigeru Kojima
发明人： Ichiro Fujiwara , Akio Machida , Shigeru Kojima
IPC分类号： G01Q60/10 , G01Q60/30 , G01Q80/00 , G11B9/00 , G11B9/02 , G11B9/06 , G11B9/08 , G11B9/14 , G11B11/08 , G11B7/00
CPC分类号： B82Y10/00 , G11B11/08 , G11B9/02 , G11B9/08 , G11B9/14 , G11B9/1409 , G11B9/1418 , Y10S977/947
摘要： A recording and reproducing apparatus has a recording and/or reading head having a tip for recording and/or reproducing information on and/or from a recording medium. Information is recorded and/or erased by way of a polarization reversal or transport of electric charges in a predetermined area of the recording medium in response to application of a pulse voltage from the head. The information recorded in the predetermined area is detected as a change in the electric charges or an electrostatic capacitance or a surface potential or their differential in the predetermined area for reproducing the information.
摘要翻译：记录和再现设备具有记录和/或读取头，其具有用于在和/或从记录介质记录和/或再现信息的提示。响应于来自头部的脉冲电压的应用，通过在记录介质的预定区域中的电荷的极化反转或传输来记录和/或擦除信息。记录在预定区域中的信息被检测为用于再现信息的电荷或静电电容或表面电位或其在预定区域中的差异的变化。

17. 发明授权

US5098851A Fabricating a semiconductor photodetector by annealing to smooth the PN junction 失效
标题翻译：通过退火制造半导体光电探测器以平滑PN结
公开(公告)号：US5098851A
公开(公告)日：1992-03-24
申请号：US474336
申请日：1990-02-02
申请人： Kazuhiro Ito , Kazuyuki Nagatsuma , Hiroshi Matsuda , Ichiro Fujiwara
发明人： Kazuhiro Ito , Kazuyuki Nagatsuma , Hiroshi Matsuda , Ichiro Fujiwara
IPC分类号： H01L31/18
CPC分类号： H01L31/184 , H01L31/1844 , H01L31/1864 , Y02E10/544 , Y02P70/521 , Y10S148/167 , Y10S438/965
摘要： A semiconductor photodetector is disclosed which comprises a pn junction formed in a semiconductor substrate and a pair of electrodes for applying a reverse bias to the pn junction, in which at least a part of the junction plane of the pn junction has been metamorphosed by enhanced diffusion. Hence the pn junction from an outer peripheral portion and a central portion is made smooth.
摘要翻译：公开了一种半导体光电检测器，其包括形成在半导体衬底中的pn结和用于向pn结施加反向偏压的一对电极，其中pn结的至少一部分结面已经被增强的扩散变质。因此，使来自外周部和中央部的pn结成为平滑的。

18. 发明授权

US07521751B2 Nonvolatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US07521751B2
公开(公告)日：2009-04-21
申请号：US11229409
申请日：2005-09-16
申请人： Ichiro Fujiwara
发明人： Ichiro Fujiwara
IPC分类号： H01L27/105
CPC分类号： H01L29/66833 , H01L21/28282 , H01L27/115 , H01L29/792
摘要： To provide a nonvolatile memory device suppressing a reduction of a data retention characteristic even if charges injected and stored into a local area of a nitride film is redistributed to achieve a reduction of voltage, the nonvolatile memory device in which hot electrons are injected into the local area of the nitride film at one or both of source•drain regions side to store data in a memory transistor is satisfied with a standard for evaluating a film quality of the nitride film, the standard being defined by one of the followings: a density of the bond group of silicon and hydrogen being under 1×1021 cm−3; an extinction coefficient in an ultraviolet region at a wavelength of 240 nm being under 0.10 or the extinction coefficient in 230 nm being under 0.14; an optical energy, a peak wavelength of an luminance spectrum, or a peak energy thereof.
摘要翻译：即使注入并存储在氮化膜的局部区域中的电荷被重新分配以实现电压的降低，也提供一种抑制数据保持特性降低的非易失性存储器件，其中将热电子注入本地的非易失性存储器件在源极区域侧的一个或两个处的氮化物膜的面积被存储在存储晶体管中以将数据存储在存储晶体管中满足用于评估氮化物膜的膜质量的标准，该标准由以下之一定义：硅和氢的键合基团在1×10 21 cm -3以下; 波长240nm的紫外线区域的消光系数在0.10以下，230nm的消光系数在0.14以下; 光能，亮度谱的峰值波长或其峰值能量。

19. 发明授权

US07259433B2 Non-volatile semiconductor memory device and method for producing same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07259433B2
公开(公告)日：2007-08-21
申请号：US11131865
申请日：2005-05-18
申请人： Kazumasa Nomoto , Hiroshi Aozasa , Ichiro Fujiwara , Shinji Tanaka
发明人： Kazumasa Nomoto , Hiroshi Aozasa , Ichiro Fujiwara , Shinji Tanaka
IPC分类号： H01L29/72
CPC分类号： H01L29/792 , H01L21/28282 , H01L21/7624
摘要： The memory device has a plurality of dielectric films including charge storage layers CS having a charge holding capability therein and stacked on an active region of a semiconductor SUB and electrodes G on the plurality of dielectric films. Each charge storage layer CS includes a first nitride film CS1 made of silicon nitride or silicon oxynitride and a second nitride film CS2 made of silicon nitride or silicon oxynitride and having a higher charge trap density than the first nitride film CS1. The first nitride film CS1 is formed by chemical vapor deposition using a first gas which contains a first silicon-containing gas containing chlorine with a predetermined percent composition and a nitrogen-containing gas as starting materials. The second nitride film CS2 is formed by chemical vapor deposition using a second gas which contains a second silicon-containing gas having a lower chlorine percent composition than the above predetermined percent composition and a nitrogen-containing gas as starting materials.
摘要翻译：存储器件具有多个电介质膜，其包括其中具有电荷保持能力的电荷存储层CS，并且堆叠在半导体SUB的有源区和多个介电膜上的电极G. 每个电荷存储层CS包括由氮化硅或氮氧化硅制成的第一氮化物膜CS 1和由氮化硅或氮氧化硅制成并且具有比第一氮化物膜CS 1更高的电荷陷阱密度的第二氮化物膜CS 2。第一氮化物膜CS1通过化学气相沉积形成，该第一气体含有含有预定百分比组成的含氯的第一含硅气体和含氮气体作为原料。第二氮化物膜CS2通过使用包含比上述预定百分比组成低的氯百分含量的第二含硅气体和含氮气体作为原料的第二气体进行化学气相沉积而形成。

20. 发明授权

US07145808B2 Nonvolatile semiconductor memory apparatus and method of producing the same 失效
公开(公告)号：US07145808B2
公开(公告)日：2006-12-05
申请号：US11079299
申请日：2005-03-15
申请人： Ichiro Fujiwara , Hiromi Nobukata
发明人： Ichiro Fujiwara , Hiromi Nobukata
IPC分类号： G11C16/06
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0491 , H01L27/105 , H01L27/115 , H01L27/11573 , H01L29/42332 , H01L29/792
摘要： A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/drain regions (S, SSL, D, SBL) formed on a semiconductor substrate (SUB, W), a charge storage film (GD) having a charge storage faculty and a gate electrode (WL). Memory peripheral circuits (2a to 9) generate a first voltage (Vd) and a second voltage (Vg-Vwell), apply the first voltage (Vd) to the second source/drain region (D, SBL) by using potential (0V) of the first source/drain region (S, SSL) as reference, apply the second voltage (Vg-Vwell) to the gate electrode (WL), generate hot electrons (HE) by ionization collision on the second source/drain region (D, SBL) side, and inject the hot electrons (HE) to the charge storage film (GD) from the second source/drain region (D, SBL) side at the time of writing data.

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