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11. 发明授权

US07486544B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07486544B2
公开(公告)日：2009-02-03
申请号：US11826636
申请日：2007-07-17
申请人： Ryo Mori , Toshio Yamada , Tetsuya Muraya
发明人： Ryo Mori , Toshio Yamada , Tetsuya Muraya
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/412
摘要： The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between the storage and complementary bit lines and whose gate is connected to a word line, a substrate bias switching circuit is provided. In normal operation, the substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed. In the standby state, the substrate bias switching circuit supplies a predetermined voltage which is lower than the power source voltage and by which a PN junction between the N-type well and the source of the P-channel MOSFET is not forward biased to the N-type well, and supplies a predetermined voltage which is higher than the ground potential and by which a PN junction between the P-type well and the source of the N-channel MOSFET is not forward biased to the P-type well.
摘要翻译：本发明提供一种半导体集成电路器件，其具有泄漏电流降低的SRAM。在包括多个存储单元的SRAM中，每个存储单元由两个反相器电路的输入和输出端子交叉存储的存储器构成，以及设置在存储和互补位线之间并且其栅极连接到字线的选择MOSFET，提供了衬底偏置开关电路。在正常操作中，衬底偏置开关电路将电源电压提供给形成存储单元的P沟道MOSFET的N型阱，并将电路的接地电位提供给P型阱，其中，形成N沟道MOSFET。在待机状态下，衬底偏置开关电路提供低于电源电压的预定电压，并且N型阱和P沟道MOSFET的源极之间的PN结未被正向偏置到N 并且提供比地电位高的预定电压，并且P型阱和N沟道MOSFET的源极之间的PN结未被正向偏置到P型阱。

12. 发明授权

US07317658B2 Semiconductor integrated circuit and IC card 失效
标题翻译：半导体集成电路和IC卡
公开(公告)号：US07317658B2
公开(公告)日：2008-01-08
申请号：US11377351
申请日：2006-03-17
申请人： Yoshio Takazawa , Toshio Yamada , Shinichi Ozawa , Takeo Kanai , Minoru Katoh , Koudou Yamauchi , Toshihiro Araki
发明人： Yoshio Takazawa , Toshio Yamada , Shinichi Ozawa , Takeo Kanai , Minoru Katoh , Koudou Yamauchi , Toshihiro Araki
IPC分类号： G11C8/00
CPC分类号： G11C5/14 , G11C7/12 , G11C7/22 , G11C17/12 , G11C2207/2227
摘要： A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.
摘要翻译：半导体集成电路具有可以进入活动状态或待机状态的存储器，并且存储器具有用于存储单元连接的位线和源极线的电压产生电路。响应于从活动状态转换到待机状态的指令，电压产生电路使位线的电位和源极线的电位彼此相等。响应于从待机状态转换到活动状态的指令，电压产生电路产生位线和源极线之间的电位差。在待机状态下，位线的电位和源极线的电位彼此相等。因此，每个存储单元的源极和漏极之间不会发生次阈值泄漏。在活动状态下，源极线电位不变。

13. 发明申请

US20070049492A1 Honeycomb catalytic body and process for manufacturing honeycomb catalytic body 有权
标题翻译：蜂窝催化体及蜂窝催化体制造工艺
公开(公告)号：US20070049492A1
公开(公告)日：2007-03-01
申请号：US11511461
申请日：2006-08-29
申请人： Yukio Miyairi , Toshio Yamada
发明人： Yukio Miyairi , Toshio Yamada
IPC分类号： B01J23/00
CPC分类号： B01J35/04 , B01J23/40 , B01J23/63 , B01J35/002 , B01J35/10 , B01J37/0215 , B01J37/343
摘要： A honeycomb catalyst body includes: porous partition walls having a large number of pores and disposed to form a plurality of cells communicating between two end faces, plugged portions disposed to plug each of the cells on one of the end faces, and catalyst layers loaded in layers on an inner surface of the cells and an inner surface of the pores and containing a noble metal. Mass (Mc) of the noble metal contained in the catalyst layer loaded on the inner surface of the cells and mass (Mp) of the noble metal contained in the catalyst layer loaded on the inner surface of the pores satisfy the relation of (Mp)/(Mc)≧4. The honeycomb catalyst body is excellent in purification efficiency, has low pressure loss, and is mountable even in a limited space.
摘要翻译：一种蜂窝状催化剂体，具有：具有多个孔的多孔分隔壁，并且设置成形成在两个端面之间连通的多个单元，设置成堵塞其中一个端面上的每个单元的堵塞部分，以及装载在在细胞的内表面上的层和孔的内表面并含有贵金属。包含在负载在电池内表面上的催化剂层中的贵金属的质量（M SUB）和催化剂中所含的贵金属的质量（M> P）填充在孔的内表面上的层满足（M p>）））/>>）= 4的关系。蜂窝状催化剂体的净化效率优异，压力损失小，即使在有限的空间也能够安装。

14. 发明申请

US20060210764A1 Ceramic honeycomb structure 审中-公开
标题翻译：陶瓷蜂窝结构
公开(公告)号：US20060210764A1
公开(公告)日：2006-09-21
申请号：US11373272
申请日：2006-03-13
申请人： Toshio Yamada , Kanji Yamada
发明人： Toshio Yamada , Kanji Yamada
IPC分类号： B32B3/12 , B21D39/00
CPC分类号： C04B38/0006 , B01D46/2444 , B01D46/2462 , B01D46/2466 , B01D2046/2433 , B01D2046/2496 , B01D2279/30 , C04B35/195 , C04B35/62625 , C04B41/009 , C04B41/5024 , C04B41/52 , C04B41/85 , C04B41/89 , C04B2111/00793 , C04B2111/0081 , C04B2235/3206 , C04B2235/3418 , C04B2235/3481 , C04B2235/5216 , C04B2235/5436 , C04B2235/5463 , C04B2235/77 , C04B2235/96 , F01N3/0222 , F01N2330/06 , Y10T428/1234 , Y10T428/24149 , C04B35/00 , C04B14/46 , C04B41/4521 , C04B41/4539 , C04B41/4582 , C04B41/5089 , C04B41/5025
摘要： A ceramic honeycomb structure includes a cell structure which includes a plurality of cells partitioned by porous partition walls and forming fluid channels, and an outer wall disposed on an outer circumferential surface of the cell structure and formed of a coating material including ceramic particles. The ceramic particles have an average particle size of 20 to 50 μm, and a portion of the outer wall positioned on an outer side of a center portion of the outer wall in its thickness direction has a porosity lower than porosity of the center portion.
摘要翻译：陶瓷蜂窝结构体包括由多孔分隔壁隔开并形成流体通道的多个单元构成的单电池结构，以及设置在电池结构体的外周面的外壁，由包含陶瓷颗粒的涂层材料形成。陶瓷颗粒的平均粒径为20〜50μm，外壁的厚度方向的中心部的外侧的一部分的外壁的孔隙率比中心部的孔隙率低。

15. 发明申请

US20060164906A1 Semiconductor integrated circuit and IC card 失效
公开(公告)号：US20060164906A1
公开(公告)日：2006-07-27
申请号：US11377351
申请日：2006-03-17
申请人： Yoshio Takazawa , Toshio Yamada , Shinichi Ozawa , Takeo Kanai , Minoru Katoh , Koudou Yamauchi , Toshihiro Araki
发明人： Yoshio Takazawa , Toshio Yamada , Shinichi Ozawa , Takeo Kanai , Minoru Katoh , Koudou Yamauchi , Toshihiro Araki
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C7/12 , G11C7/22 , G11C17/12 , G11C2207/2227
摘要： A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

16. 发明授权

US07008461B2 Honeycomb structure, method for manufacturing honeycomb structure, and exhaust gas purification system using honeycomb structure 有权
标题翻译：蜂窝结构，蜂窝结构体的制造方法以及使用蜂窝结构的废气净化系统
公开(公告)号：US07008461B2
公开(公告)日：2006-03-07
申请号：US10668195
申请日：2003-09-24
申请人： Tatsuyuki Kuki , Toshio Yamada
发明人： Tatsuyuki Kuki , Toshio Yamada
IPC分类号： B01D46/00 , B32B3/12
CPC分类号： B01D46/247 , B01D46/2451 , B01D46/2459 , B01D46/2466 , B01D46/2474 , B01D2046/2477 , B01D2046/2481 , B01D2046/2488 , B01D2046/2492 , B01D2046/2496 , B01J35/04 , B29C70/766 , C04B38/0006 , F01N3/0222 , F01N2260/16 , F01N2330/06 , F01N2330/30 , Y02T10/20 , Y10S55/05 , Y10S55/10 , Y10S55/30 , Y10S264/48 , Y10T428/24149 , Y10T428/24157 , C04B35/10 , C04B35/18 , C04B35/185 , C04B35/195 , C04B35/565 , C04B35/584 , C04B38/0012 , C04B38/061 , C04B38/065
摘要： There is disclosed a honeycomb structure usable as a filter for trapping/collecting particulates included in an exhaust gas; and the structure can remove ashes deposited inside without requiring any special mechanism or apparatus or without being detached from the exhaust system. The structure includes: a plurality of through channels 9 extending to the axial direction of the honeycomb structure, porous partition walls 7 separating through channels one another, and plugging portions 11 plugging predetermined through channels 9a at one end and the rest of through channels 9b at other end opposite to the plugged end of the predetermined through channels, wherein a through-hole is formed in at least a part of the plugging portion, and its diameter is 0.2 mm or more, but not more than a value which is smaller between 1 mm and 75% of a diameter of an inscribed circle of the through channel.
摘要翻译：公开了一种可用作捕集/收集废气中所含的微粒的过滤器的蜂窝结构体; 并且该结构可以除去沉积在内部的灰烬，而不需要任何特殊的机构或装置，或者不从排气系统脱离。该结构包括：沿蜂窝结构的轴向方向延伸的多个通道9，通过相互分离的多孔分隔壁7，以及通过一端的通道9a和预定通过通道9的其余部分堵塞的堵塞部分11 b在与预定通孔的堵塞端相对的另一端处，其中在堵塞部分的至少一部分中形成通孔，其直径为0.2mm以上，但不大于较小的值在通孔的内切圆的直径的1毫米和75％之间。

17. 发明申请

US20060023520A1 Semiconductor integrated circuit device 失效
公开(公告)号：US20060023520A1
公开(公告)日：2006-02-02
申请号：US11169800
申请日：2005-06-30
申请人： Ryo Mori , Toshio Yamada , Tetsuya Muraya
发明人： Ryo Mori , Toshio Yamada , Tetsuya Muraya
IPC分类号： G11C5/14
CPC分类号： G11C11/412
摘要： The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between the storage and complementary bit lines and whose gate is connected to a word line, a substrate bias switching circuit is provided. In normal operation, the substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed. In the standby state, the substrate bias switching circuit supplies a predetermined voltage which is lower than the power source voltage and by which a PN junction between the N-type well and the source of the P-channel MOSFET is not forward biased to the N-type well, and supplies a predetermined voltage which is higher than the ground potential and by which a PN junction between the P-type well and the source of the N-channel MOSFET is not forward biased to the P-type well.

18. 发明授权

US06242071B1 Method for assembling ceramic honeycomb structure, and supporting member therefor 有权
标题翻译：陶瓷蜂窝结构体的组装方法及其支撑构件
公开(公告)号：US06242071B1
公开(公告)日：2001-06-05
申请号：US09271156
申请日：1999-03-17
申请人： Toshio Yamada , Toshihiko Hijikata , Mikio Tanaka
发明人： Toshio Yamada , Toshihiko Hijikata , Mikio Tanaka
IPC分类号： B32B312
CPC分类号： F01N3/2853 , B01J35/04 , F01N3/2864 , F01N3/2889 , F01N2330/06 , F01N2450/02 , F23J2219/10 , Y10T29/49844 , Y10T29/49863 , Y10T29/49908 , Y10T29/49938 , Y10T428/236 , Y10T428/24149
摘要： To provide a durable catalytic converter or heat exchanger to be used in an exhaust gas cleaning-up system for an internal combustion engine or the like. A durable catalytic converter, heat exchanger or the like is provided by use of a supporting member provided with a low-friction layer to smoothly assemble a ceramic honeycomb structure in a metallic can.
摘要翻译：提供一种用于内燃机等的排气净化系统中使用的耐用催化转化器或热交换器。耐久性催化转化器，热交换器等通过使用具有低摩擦层以在金属罐中平稳地组装陶瓷蜂窝结构。

19. 发明授权

US6005401A Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method 失效
标题翻译：用于连接半导体晶片和探针端子的IC端子的半导体晶片封装，方法和装置，半导体集成电路的测试方法，探针卡及其制造方法
公开(公告)号：US6005401A
公开(公告)日：1999-12-21
申请号：US837954
申请日：1997-04-14
申请人： Yoshirou Nakata , Toshio Yamada , Atsushi Fujiwara , Isao Miyanaga , Shin Hashimoto , Yukiharu Uraoka , Yasushi Okuda , Kenzou Hatada
发明人： Yoshirou Nakata , Toshio Yamada , Atsushi Fujiwara , Isao Miyanaga , Shin Hashimoto , Yukiharu Uraoka , Yasushi Okuda , Kenzou Hatada
IPC分类号： G01R1/04 , G01R1/073 , G01R31/28 , H01L21/66
CPC分类号： G01R31/2886 , G01R1/0491 , G01R31/2867 , G01R31/2831
摘要： A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.
摘要翻译：提供了一种保持板，其具有多个用于测试半导体芯片的集成电路端子的半导体晶片，与具有电连接到其相应的集成电路端子的多个探针端子的探针片相对。具有与多个探针端子电连接的布线的绝缘基板设置在与保持板相对的探针片上。在探针片和绝缘基片之间插入弹性部件。保持板和探针片的关系使得由保持板保持的半导体晶片的每个集成电路端子电连接到其对应的探针片的探针端子。

20. 发明授权

US5910010A Semiconductor integrated circuit device, and process and apparatus for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法和装置
公开(公告)号：US5910010A
公开(公告)日：1999-06-08
申请号：US732215
申请日：1997-02-18
申请人： Hirotaka Nishizawa , Tomoyoshi Miura , Ichirou Anjou , Masamichi Ishihara , Masahiro Yamamura , Sadao Morita , Takashi Araki , Kiyoshi Inoue , Toshio Sugano , Tetsuji Kohara , Toshio Yamada , Yasushi Sekine , Yoshiaki Anata , Masakatsu Goto , Norihiko Kasai , Shinobu Takeura , Mutsuo Tsukuda , Yasunori Yamaguchi , Jiro Sawada , Hidetoshi Iwai , Seiichiro Tsukui , Tadao Kaji , Noboru Shiozawa
发明人： Hirotaka Nishizawa , Tomoyoshi Miura , Ichirou Anjou , Masamichi Ishihara , Masahiro Yamamura , Sadao Morita , Takashi Araki , Kiyoshi Inoue , Toshio Sugano , Tetsuji Kohara , Toshio Yamada , Yasushi Sekine , Yoshiaki Anata , Masakatsu Goto , Norihiko Kasai , Shinobu Takeura , Mutsuo Tsukuda , Yasunori Yamaguchi , Jiro Sawada , Hidetoshi Iwai , Seiichiro Tsukui , Tadao Kaji , Noboru Shiozawa
IPC分类号： H01L21/56 , H01L21/98 , H01L23/495 , H01L25/065 , H01L21/52 , H01L21/58 , H01L21/60
CPC分类号： H01L24/06 , H01L21/565 , H01L23/4951 , H01L23/49575 , H01L25/0657 , H01L25/50 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/4826 , H01L2224/49171 , H01L2224/73215 , H01L2225/06527 , H01L2225/06551 , H01L2225/06582 , H01L2225/06586 , H01L2225/06589 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01055 , H01L2924/01058 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025 , H01L2924/351
摘要： A method of manufacturing a semiconductor integrated circuit device includes the steps of constructing a plurality of lead frames having leads which each include an inner portion and an outer portion and electrically connecting a semiconductor chip to the inner portions of the leads of each frame. The lead frames are then stacked one above each other to form a vertical stack and plates are then inserted between each of the lead frames with each plate having an opening in the center whereby a central cavity is formed in the stack. The stack is then placed between a top mold member and a bottom mold member and a resin is injected into the central cavity whereupon the resin is cured to form a single resin package encapsulating the semiconductor chips. The resin package is then released from the mold members.
摘要翻译： PCT No.PCT / JP95 / 00662 Sec。 371日期1997年2月18日 102（e）日期1997年2月18日PCT提交1995年4月5日PCT公布。 WO95 / 29506 PCT公开号日期：1995年11月2日制造半导体集成电路器件的方法包括以下步骤：构造多个引线框架，引线框架各自包括内部部分和外部部分，并将半导体芯片电连接到引线的内部每一帧。然后将引线框架彼此堆叠以形成垂直堆叠，然后将板在每个引线框架之间插入，每个板在中心具有开口，由此在堆叠中形成中心空腔。然后将堆叠放置在顶模构件和底模构件之间，并将树脂注入到中心腔中，由此树脂固化以形成封装半导体芯片的单个树脂封装。然后将树脂包装从模具部件中释放出来。

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