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    • 11. 发明授权
    • Semiconductor device including transistors having different drain breakdown voltages on a single substrate
    • 半导体器件包括在单个衬底上具有不同漏极击穿电压的晶体管
    • US07375409B2
    • 2008-05-20
    • US10892459
    • 2004-07-15
    • Yoko Sato
    • Yoko Sato
    • H01L27/088
    • H01L21/76283H01L27/1203
    • A semiconductor device is provided comprising a supporting substrate, an insulating layer on the substrate, and a first semiconductor layer on the insulating layer. A first high breakdown-voltage transistor is formed in the first semiconductor layer, a second semiconductor layer is formed on the insulating layer and a second high breakdown-voltage transistor is formed in the second semiconductor layer. A first element isolation region reaching the insulating layer is provided between the first and second semiconductor layers. A third semiconductor layer is formed on the insulating layer, a first low breakdown-voltage transistor is formed in the third semiconductor layer, a second low breakdown-voltage transistor is formed in the third semiconductor layer, and a second element isolation region not reaching the insulating layer is formed in the third semiconductor layer between the first and second low breakdown-voltage transistors. The first element isolation region comprises a dual-trench insulating layer.
    • 提供了一种半导体器件,包括支撑衬底,衬底上的绝缘层和绝缘层上的第一半导体层。 在第一半导体层中形成第一高击穿电压晶体管,在绝缘层上形成第二半导体层,在第二半导体层中形成第二高击穿电压晶体管。 到达绝缘层的第一元件隔离区域设置在第一和第二半导体层之间。 在绝缘层上形成第三半导体层,在第三半导体层中形成第一低击穿电压晶体管,在第三半导体层中形成第二低击穿电压晶体管,在第二半导体层中形成第二低击穿电压晶体管, 绝缘层形成在第一和第二低击穿电压晶体管之间的第三半导体层中。 第一元件隔离区域包括双沟槽绝缘层。
    • 17. 发明申请
    • Semiconductor device and method of manufacturing the same
    • 半导体装置及其制造方法
    • US20050056908A1
    • 2005-03-17
    • US10892459
    • 2004-07-15
    • Yoko Sato
    • Yoko Sato
    • H01L21/76H01L21/762H01L21/8234H01L21/8238H01L27/08H01L27/088H01L27/092H01L27/12H01L29/786H01L29/00
    • H01L21/76283H01L27/1203
    • A semiconductor device is provided comprising a supporting substrate, an insulating layer on the substrate, and a first semiconductor layer on the insulating layer. A first high breakdown-voltage transistor is formed in the first semiconductor layer, a second semiconductor layer is formed on the insulating layer and a second high breakdown-voltage transistor is formed in the second semiconductor layer. A first element isolation region reaching the insulating layer is provided between the first and second semiconductor layers. A third semiconductor layer is formed on the insulating layer, a first low breakdown-voltage transistor is formed in the third semiconductor layer, a second low breakdown-voltage transistor is formed in the third semiconductor layer, and a second element isolation region not reaching the insulating layer is formed in the third semiconductor layer between the first and second low breakdown-voltage transistors. The first element isolation region comprises a dual-trench insulating layer.
    • 提供了一种半导体器件,包括支撑衬底,衬底上的绝缘层和绝缘层上的第一半导体层。 在第一半导体层中形成第一高击穿电压晶体管,在绝缘层上形成第二半导体层,在第二半导体层中形成第二高击穿电压晶体管。 到达绝缘层的第一元件隔离区域设置在第一和第二半导体层之间。 在绝缘层上形成第三半导体层,在第三半导体层中形成第一低击穿电压晶体管,在第三半导体层中形成第二低击穿电压晶体管,在第二半导体层中形成第二低击穿电压晶体管, 绝缘层形成在第一和第二低击穿电压晶体管之间的第三半导体层中。 第一元件隔离区域包括双沟槽绝缘层。
    • 18. 发明授权
    • Methods for making semiconductor devices
    • 制造半导体器件的方法
    • US06709908B2
    • 2004-03-23
    • US09791984
    • 2001-02-23
    • Yoko SatoAkihiko Ebina
    • Yoko SatoAkihiko Ebina
    • H01L2184
    • H01L21/76264H01L21/76281H01L27/1203
    • Certain embodiments relate to methods for making a semiconductor device that inhibit the formation of a parasitic device. A method for making a semiconductor device includes a delimiting step and a dopant implantation step. The delimiting step partially oxidizes a single-crystal silicon layer provided on a semiconductor substrate 11 with an insulating layer therebetween to form a plurality of isolated single-crystal-silicon-layer segments 13a delimited by the insulating layer 16. In the implantation step, dopant ions 18 are implanted into the single-crystal-silicon-layer segments 13a to activate the single-crystal-silicon-layer segments 13a. In this implantation step, the dopant is implanted into the single-crystal-silicon-layer segments 13a by an implantation energy which is set so that the position of the maximum of the dopant concentration lies at bottom edges Ea and Eb of each single-crystal-silicon-layer segment 13a.
    • 某些实施例涉及制造抑制寄生器件形成的半导体器件的方法。 制造半导体器件的方法包括限定步骤和掺杂剂注入步骤。 定界步骤部分氧化设置在半导体衬底11上的单晶硅层,其间具有绝缘层,以形成由绝缘层16限定的多个隔离的单晶硅层段13a。在注入步骤中,掺杂剂 将离子18注入到单晶硅层段13a中以激活单晶硅层段13a。 在该注入步骤中,通过注入能量将掺杂剂注入到单晶硅层段13a中,所述注入能量被设定为使得掺杂剂浓度的最大值的位置位于每个单晶的底部边缘Ea和Eb 硅层段13a。