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11. 发明授权

US07904617B2 Indicating data buffer by last bit flag 失效
标题翻译：用最后一位标志指示数据缓冲区
公开(公告)号：US07904617B2
公开(公告)日：2011-03-08
申请号：US12100739
申请日：2008-04-10
申请人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： G06F5/00 , G06F15/16
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3018 , H04L49/90 , H04L49/9094
摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one” or “zero” and indicates when the data buffer having the last bit is transmitted. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.
摘要翻译：提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。每个控制块具有最后一位特征，其是可设置为“一”或“零”的单个位，并且指示何时发送具有最后位的数据缓冲器。当附加数据缓冲器被链接到先前的数据缓冲器，指示要发送附加数据缓冲器时，最后一位处于第一位置，而当没有附加数据缓冲器被链接到先前数据缓冲器时，最后一位处于第一位置。最后一位的位置被传送到指示特定帧的结束的网络处理器。

12. 发明授权

US07072347B2 Assignment of packet descriptor field positions in a network processor 失效
公开(公告)号：US07072347B2
公开(公告)日：2006-07-04
申请号：US09792494
申请日：2001-02-23
申请人： Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L49/90 , H04L47/50 , H04L49/901
摘要： A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.

13. 发明授权

US07627701B2 Indicating last data buffer by last bit flag bit 有权
标题翻译：用最后一位标志位指示最后一个数据缓冲区
公开(公告)号：US07627701B2
公开(公告)日：2009-12-01
申请号：US12120419
申请日：2008-05-14
申请人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： G06F5/00 , G06F15/16
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3018 , H04L49/90 , H04L49/9094
摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.
摘要翻译：提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器的特定框架。

14. 发明授权

US07506081B2 System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memories 失效
标题翻译：从低带宽存储器维持数据管道的高带宽需求的系统和方法
公开(公告)号：US07506081B2
公开(公告)日：2009-03-17
申请号：US10850219
申请日：2004-05-20
申请人： Peter Irma August Barri , Jean Louis Calvignac , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken , Miroslav Vrana
发明人： Peter Irma August Barri , Jean Louis Calvignac , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken , Miroslav Vrana
IPC分类号： G06F3/00
CPC分类号： G11C7/1066 , G11C7/1039 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C11/4093
摘要： A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory sub-system includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR DRAM or simultaneously from a plurality of the DDR DRAMs. By controlling the DDR DRAMs so that the outputs provide data serially or in parallel, the data Bandwidth is adjustable over a wide range. Similarly, data is written serially into one DDR DRAM or simultaneously into multiple DDR DRAMs. As a consequence buffers with data from the same frame are written into or read from different DDR DRAMs.
摘要翻译：网络处理器包括胖管端口和存储器子系统，其提供足够的数据以满足胖管端口的带宽要求。存储器子系统包括被控制的多个DDR DRAM，从而从一个DDR DRAM提取数据或者同时从多个DDR DRAM中提取数据。通过控制DDR DRAM，使得输出串行或并行提供数据，数据带宽可在宽范围内调节。类似地，数据被串行地写入一个DDR DRAM或同时被写入多个DDR DRAM。因此，来自相同帧的数据的缓冲器被写入或从不同的DDR DRAM中读取。

15. 发明授权

US07130916B2 Linking frame data by inserting qualifiers in control blocks 失效
公开(公告)号：US07130916B2
公开(公告)日：2006-10-31
申请号：US09791336
申请日：2001-02-23
申请人： Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： G06F15/167 , G06F12/00 , G06F12/16 , G06F13/28 , G06F9/44 , H04L12/54 , G06F15/16 , G06F12/14 , G06F13/00 , G06F3/00 , G06F9/46
CPC分类号： H04L49/3081 , G06F13/4243 , H04L2012/5681
摘要： A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.

16. 发明授权

US06910092B2 Chip to chip interface for interconnecting chips 失效
标题翻译：用于互连芯片的芯片到芯片接口
公开(公告)号：US06910092B2
公开(公告)日：2005-06-21
申请号：US10016800
申请日：2001-12-10
申请人： Jean Louis Calvignac , Marco Heddes , Kerry Christopher Imming , Joseph Franklin Logan , Tolga Ozguner
发明人： Jean Louis Calvignac , Marco Heddes , Kerry Christopher Imming , Joseph Franklin Logan , Tolga Ozguner
IPC分类号： G06F13/00 , G06F13/14 , G06F13/42
CPC分类号： G06F13/4265
摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure. Communications between the chips are provided by a pair of Chip to Chip Macros, one of each operatively positioned on one of the chips, and a Chip to Chip Bus Interface operatively coupling the Chip to Chip Macros.
摘要翻译：网络处理器（NP）由多个可操作耦合的芯片形成。 NP包括耦合到耦合到数据流芯片的数据流芯片和数据存储存储器的网络处理器复合（NPC）芯片。可选的调度器芯片耦合到数据流芯片。命名的组件被复制以创建对称的入口和出口结构。芯片之间的通信由一对芯片到芯片宏提供，其中每一个可操作地位于一个芯片上，并且芯片到芯片总线接口可操作地将芯片连接到芯片宏。

17. 发明授权

US06836480B2 Data structures for efficient processing of multicast transmissions 有权
标题翻译：用于多播传输的高效处理的数据结构
公开(公告)号：US06836480B2
公开(公告)日：2004-12-28
申请号：US09839079
申请日：2001-04-20
申请人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： H04L1256
CPC分类号： H04L49/901 , H04L12/1881 , H04L47/10 , H04L47/20 , H04L49/90
摘要： Data structures, a method, and an associated transmission system for multicast transmission on network processors in order both to minimize multicast transmission memory requirements and to account for port performance discrepancies. Frame data for multicast transmission on a network processor is read into buffers to which are associated various control structures and a reference frame. The reference frame and the associated control structures permit multicast targets to be serviced without creating multiple copies of the frame. Furthermore this same reference frame and control structures allow buffers allocated for each multicast target to be returned to the free buffer queue without waiting until all multicast transmissions are complete.
摘要翻译：数据结构，方法和相关的传输系统，用于网络处理器上的组播传输，以便最大限度地减少组播传输内存的需求并解决端口性能差异。将网络处理器上的组播传输的帧数据读入与各种控制结构和参考帧相关联的缓冲器。参考帧和相关联的控制结构允许在不创建帧的多个拷贝的情况下对多播目标进行服务。此外，相同的参考帧和控制结构允许为每个多播目标分配的缓冲区返回到空闲缓冲器队列，而不等待所有多播传输完成。

18. 发明授权

US5737524A Add-in board with programmable configuration registers for use in PCI bus computers 失效
标题翻译：附加板与可编程配置寄存器用于PCI总线计算机
公开(公告)号：US5737524A
公开(公告)日：1998-04-07
申请号：US446390
申请日：1995-05-22
申请人： Ariel Cohen , William Gavin Holland , Joseph Franklin Logan , Avi Parash
发明人： Ariel Cohen , William Gavin Holland , Joseph Franklin Logan , Avi Parash
IPC分类号： G06F13/36 , G06F13/14 , G06F15/177 , G06F13/00
CPC分类号： G06F15/177
摘要： An adapter or add-in card for using in a peripheral component interconnect (PCI) computer includes a universal module which couples the card to the PCI bus. The module includes a set of selectively programmable configuration registers which are loaded by a microprocessor on the adapter. A circuit arrangement on the module issues a command which inhibits the PCI processor from accessing the configuration registers until fully loaded.
摘要翻译：用于在外围组件互连（PCI）计算机中使用的适配器或附加卡包括将卡耦合到PCI总线的通用模块。该模块包括一组选择性可编程配置寄存器，它们由适配器上的微处理器加载。模块上的电路布置发出一个命令，禁止PCI处理器访问配置寄存器，直到完全加载。

19. 发明申请

US20080222324A1 SYSTEM METHOD STRUCTURE IN NETWORK PROCESSOR THAT INDICATES LAST DATA BUFFER OF FRAME PACKET BY LAST FLAG BIT THAT IS EITHER IN FIRST OR SECOND POSITION 有权
标题翻译：网络处理器中的系统方法结构显示最后一个标记位的帧数据缓冲区的第一个或第二个位置
公开(公告)号：US20080222324A1
公开(公告)日：2008-09-11
申请号：US12120419
申请日：2008-05-14
申请人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： G06F5/00
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3018 , H04L49/90 , H04L49/9094
摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.
摘要翻译：提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器的特定框架。

20. 发明授权

US07293158B2 Systems and methods for implementing counters in a network processor with cost effective memory 失效
标题翻译：在具有成本效益的存储器的网络处理器中实现计数器的系统和方法
公开(公告)号：US07293158B2
公开(公告)日：2007-11-06
申请号：US11070060
申请日：2005-03-02
申请人： Jean Louis Calvignac , Chih-jen Chang , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Chih-jen Chang , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： G06F15/00 , G06F12/00
CPC分类号： H04L49/901 , H04L49/90
摘要： Systems and methods for implementing counters in a network processor with cost effective memory are disclosed. Embodiments include systems and methods for implementing counters in a network processor using less expensive memory such as DRAM. A network processor receives packets and implements accounting functions including counting packets in each of a plurality of flow queues. Embodiments include a counter controller that may increment counter values more than once during a R-M-W cycle. Each time a counter controller receives a request to update a counter during a R-M-W cycle that has been initiated for the counter, the counter controller increments the counter value received from memory. The incremented value is written to memory during the write cycle of the R-M-W cycle. A write disable unit disables writes that would otherwise occur during R-M-W cycles initiated for the counter during the earlier initiated R-M-W cycle.
摘要翻译：公开了在具有成本效益的存储器的网络处理器中实现计数器的系统和方法。实施例包括用于在使用诸如DRAM的廉价存储器的网络处理器中实现计数器的系统和方法。网络处理器接收分组并实现计费功能，包括在多个流队列中的每一个中计数分组。实施例包括可以在R-M-W周期期间多次增加计数器值的计数器控制器。每当计数器控制器在已经为计数器启动的R-M-W周期期间接收到更新计数器的请求时，计数器控制器递增从存储器接收的计数器值。在R-M-W周期的写周期期间，递增的值被写入存储器。写禁止单元禁用在较早启动的R-M-W周期期间为计数器启动的R-M-W周期期间将发生的写入。

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