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11. 发明授权

US07986033B2 Three-dimensional multichip module 有权
标题翻译：三维多芯片模块
公开(公告)号：US07986033B2
公开(公告)日：2011-07-26
申请号：US12124335
申请日：2008-05-21
申请人： Hans-Joachim Barth
发明人： Hans-Joachim Barth
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/34 , H01L2225/06513 , H01L2225/06589 , H01L2924/0002 , H01L2924/01079 , H01L2924/00
摘要： A three-dimensional multichip module includes a first integrated circuit chip having at least one first high-temperature functional area and one first low-temperature functional area, and at least one second integrated circuit chip having a second high-temperature functional area and a second low-temperature functional area. The second high-temperature functional area is arranged opposite the first low-temperature functional area. As an alternative, at least one low-temperature chip having only one low-temperature functional area can also be arranged between the first and second chips.
摘要翻译：三维多芯片模块包括具有至少一个第一高温功能区和一个第一低温功能区的第一集成电路芯片和至少一个具有第二高温功能区和第二高温功能区的第二集成电路芯片低温功能区。第二高温功能区与第一低温功能区相对。作为替代，也可以在第一和第二芯片之间设置至少一个仅具有一个低温功能区的低温芯片。

12. 发明授权

US07948064B2 System on a chip with on-chip RF shield 有权
标题翻译：片上系统采用片上RF屏蔽
公开(公告)号：US07948064B2
公开(公告)日：2011-05-24
申请号：US12242698
申请日：2008-09-30
申请人： Hans-Joachim Barth , Andre Hanke , Snezana Jenei , Oliver Nagy , Jiro Morinaga , Bernd Adler , Heinrich Koerner
发明人： Hans-Joachim Barth , Andre Hanke , Snezana Jenei , Oliver Nagy , Jiro Morinaga , Bernd Adler , Heinrich Koerner
IPC分类号： H01L23/552 , H01L21/71
CPC分类号： H01L21/71 , H01L23/49822 , H01L23/552 , H01L23/585 , H01L23/66 , H01L2224/05572 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2224/16227 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要： Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.
摘要翻译：公开了一种芯片上的系统的结构。在一个实施例中，芯片上的系统（SoC）包括设置在基板的第一部分上的RF部件，设置在基板的第二部分上的半导体部件，共享公共边界的半导体部件和RF部件，以及布置成围绕RF部件的导电笼。导电笼罩半导体元件不受来自RF电路的电磁辐射。

13. 发明申请

US20100176479A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100176479A1
公开(公告)日：2010-07-15
申请号：US12354480
申请日：2009-01-15
申请人： Sergei Postnikov , Thomas Schulz , Hans-Joachim Barth , Klaus von Arnim
发明人： Sergei Postnikov , Thomas Schulz , Hans-Joachim Barth , Klaus von Arnim
IPC分类号： H01L29/68 , H01L21/762
CPC分类号： H01L27/11 , G03F7/40 , G03F7/7035 , H01L21/32139
摘要： A method of fabricating a semiconductor device including depositing a hardmask layer on a layer of the semiconductor device, selectively etching a pattern of continuous lines in the hardmask layer, depositing an antireflective coating over remaining portions of the hardmask layer, depositing a photoresist layer on the antireflective coating, patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, and with each isolation trench having an initial width. The method further includes reducing the width of each of the isolation trenches from the initial width to desired width via a shrinking process, etching the antireflective coating underlying the isolation trenches to expose intersecting portions of the underlying continuous lines, and etching the exposed intersecting portions of the underlying continuous lines of the hardmask layer to form a pattern of line segments having line ends separated by the desired width.
摘要翻译：一种制造半导体器件的方法，包括在半导体器件的层上沉积硬掩模层，选择性地蚀刻硬掩模层中的连续线的图案，在硬掩模层的剩余部分上沉积抗反射涂层，将光致抗蚀剂层沉积在抗反射涂层，通过光刻工艺用多个隔离沟槽图案化光致抗蚀剂层，每个隔离沟槽垂直于并交叉下层硬掩模层的至少一条连续线的部分延伸，并且每个隔离沟槽具有初始宽度。该方法还包括通过收缩过程将每个隔离沟槽的宽度从初始宽度减小到期望宽度，蚀刻隔离沟槽下方的抗反射涂层以暴露下面的连续线的相交部分，并蚀刻暴露的相交部分硬掩模层的下面的连续线以形成具有以期望宽度分隔的线端部的线段的图案。

14. 发明授权

US07755196B2 Method for production of an integrated circuit bar arrangement, in particular comprising a capacitor assembly, as well as an integrated circuit arrangement 有权
标题翻译：一种用于制造集成电路板布置的方法，特别地包括电容器组件以及集成电路装置
公开(公告)号：US07755196B2
公开(公告)日：2010-07-13
申请号：US11857944
申请日：2007-09-19
申请人： Hans-Joachim Barth , Jurgen Holz
发明人： Hans-Joachim Barth , Jurgen Holz
IPC分类号： H01L23/48
CPC分类号： H01L23/5223 , H01L23/53238 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/48463 , H01L2924/14 , H01L2924/00
摘要： A method for production of an integrated circuit arrangement which contains a capacitor. A dielectric layer is structured with the aid of a two-stage etching process, and with the aid of a hard mask. In the case of an electrically insulating hard mask, the hard mask is removed again. In the case of an electrically conductive hard mask, parts of the hard mask may remain in the circuit arrangement.
摘要翻译：一种用于制造包含电容器的集成电路装置的方法。借助于两层蚀刻工艺，借助于硬掩模来构造电介质层。在电绝缘硬掩模的情况下，再次去除硬掩模。在导电硬掩模的情况下，硬掩模的部分可能保留在电路装置中。

15. 发明申请

US20100127390A1 Cooling Structures and Methods 有权
标题翻译：冷却结构与方法
公开(公告)号：US20100127390A1
公开(公告)日：2010-05-27
申请号：US12275731
申请日：2008-11-21
申请人： Hans-Joachim Barth
发明人： Hans-Joachim Barth
IPC分类号： H01L23/473 , F28F7/00 , B23P17/00 , H01L23/467
CPC分类号： H01L23/473 , H01L2924/0002 , Y10T29/49002 , H01L2924/00
摘要： Cooling structures and methods, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a cooling structure for a semiconductor device includes at least one channel defined between a first workpiece and a second workpiece. The second workpiece is bonded to the first workpiece. The at least one channel is adapted to retain a fluid.
摘要翻译：公开了冷却结构和方法，制造半导体器件的方法和半导体器件。在一个实施例中，用于半导体器件的冷却结构包括限定在第一工件和第二工件之间的至少一个通道。第二工件结合到第一工件。至少一个通道适于保持流体。

16. 发明申请

US20080290459A1 MIM Capacitors 有权
标题翻译： MIM电容器
公开(公告)号：US20080290459A1
公开(公告)日：2008-11-27
申请号：US12182901
申请日：2008-07-30
申请人： Hans-Joachim Barth , Petra Felsner , Erdem Kaltalioglu , Gerald R. Friese
发明人： Hans-Joachim Barth , Petra Felsner , Erdem Kaltalioglu , Gerald R. Friese
IPC分类号： H01L29/92
CPC分类号： H01L28/40 , H01L21/28568 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/0805 , H01L28/55 , H01L28/75
摘要： A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.
摘要翻译：一种用于形成MIM电容器的方法和由其形成的MIM电容器器件。优选实施例包括在包括MIM电容器底板的晶片上选择性地形成第一盖层，以及在MIM电容器底板上沉积绝缘层。用MIM电容器顶板图案对绝缘层进行构图，并且在图案化绝缘层上沉积MIM电介质材料。在MIM介电材料上沉积导电材料，并且平坦化晶片以从绝缘层的顶表面去除导电材料和MIM电介质材料，并形成MIM电容器顶板。在MIM电容器顶板上选择性地形成第二盖层。

17. 发明申请

US20070155090A1 Corresponding capacitor arrangement and method for making the same 有权
标题翻译：相应的电容器布置及其制造方法
公开(公告)号：US20070155090A1
公开(公告)日：2007-07-05
申请号：US11652157
申请日：2007-01-11
申请人： Hans-Joachim Barth , Helmut Tews
发明人： Hans-Joachim Barth , Helmut Tews
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability.
摘要翻译：本发明涉及一种用于制造电容器装置的方法和相应的电容器装置，其中第一绝缘层形成在载体衬底的表面，并且在所述绝缘体中产生具有多个间隔第一互连的第一电容器电极层。使用掩模层，为了揭露多个第一互连的目的，除去第一绝缘层的部分区域，并且在未覆盖的第一互连件的表面上形成电容器电介质之后，形成第二电容器电极位于涂覆有电容器电介质的第一互连之间的间隔第二互连的多重性。这种另外简化的制造方法能够实现具有每单位面积的高电容和机械稳定性的电容器的自对准和成本有效的生产。

18. 发明申请

US20070042542A1 Method for fabricating an interconnect arrangement with increased capacitive coupling and associated interconnect arrangement 有权
标题翻译：用于制造具有增加的电容耦合和相关联的互连布置的互连装置的方法
公开(公告)号：US20070042542A1
公开(公告)日：2007-02-22
申请号：US11205767
申请日：2005-08-16
申请人： Hans-Joachim Barth , Jurgen Holz
发明人： Hans-Joachim Barth , Jurgen Holz
IPC分类号： H01L21/8242
CPC分类号： H01L23/5223 , H01L21/2885 , H01L21/76877 , H01L27/0805 , H01L28/75 , H01L2924/0002 , H01L2924/3011 , H05K1/162 , H05K3/107 , H01L2924/00
摘要： A method for fabricating an interconnect arrangement with increased capacitive coupling is described. A trench structure is formed in a first dielectric having a capacitor region with a first aspect ratio and an interconnect region with a second aspect ratio connected thereto. The trench structure of the interconnect region is completely filled by a first interconnect. The trench structure of the capacitor region is only partially filled by a first capacitor electrode and is completely filled by a capacitor dielectric and a second capacitor electrode. In a second dielectric formed thereon, a second interconnect with a contact via is formed, which is connected to the second capacitor electrode.
摘要翻译：描述了一种用于制造具有增加的电容耦合的互连装置的方法。在具有第一纵横比的电容器区域和与其连接的第二纵横比的互连区域的第一电介质中形成沟槽结构。互连区域的沟槽结构由第一互连完全填充。电容器区域的沟槽结构仅由第一电容器电极部分地填充，并且由电容器电介质和第二电容器电极完全填充。在其上形成的第二电介质中，形成具有接触通孔的第二互连件，其连接到第二电容器电极。

19. 发明申请

US20060202345A1 Barrier layers for conductive features 有权
标题翻译：阻挡层用于导电特征
公开(公告)号：US20060202345A1
公开(公告)日：2006-09-14
申请号：US11079738
申请日：2005-03-14
申请人： Hans-Joachim Barth , Juergen Holz
发明人： Hans-Joachim Barth , Juergen Holz
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76873 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L2221/1089 , H01L2924/0002 , Y10T428/24479 , H01L2924/00
摘要： Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material is deposited on sidewalls of the insulating material, wherein the second barrier material is different than the first barrier material. The first barrier material induces grain growth of a subsequently deposited conductive material at a first rate, and the second barrier material induces grain growth of the conductive material at a second rate, wherein the second rate is slower than the first rate.
摘要翻译：公开了用于导电特征的阻挡层及其形成方法。第一阻挡材料沉积在绝缘材料的顶表面上，并且第二阻挡材料沉积在绝缘材料的侧壁上，其中第二阻挡材料不同于第一阻挡材料。第一阻挡材料以第一速率诱导随后沉积的导电材料的晶粒生长，并且第二阻挡材料以第二速率诱导导电材料的晶粒生长，其中第二速率比第一速率慢。

20. 发明申请

US20060019483A1 Method for production of an integrated circuit arrangement, in particular with a capacitor arrangement, as well as an integrated circuit arrangement 有权
标题翻译：用于制造集成电路装置的方法，特别是用于电容器装置，以及集成电路装置
公开(公告)号：US20060019483A1
公开(公告)日：2006-01-26
申请号：US11181574
申请日：2005-07-14
申请人： Hans-Joachim Barth , Jurgen Holz
发明人： Hans-Joachim Barth , Jurgen Holz
IPC分类号： H01L21/4763 , H01L21/302
CPC分类号： H01L23/5223 , H01L23/53238 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/48463 , H01L2924/14 , H01L2924/00
摘要： A method for production of an integrated circuit arrangement which contains a capacitor. A dielectric layer is structured with the aid of a two-stage etching process, and with the aid of a hard mask. In the case of an electrically insulating hard mask, the hard mask is removed again. In the case of an electrically conductive hard mask, parts of the hard mask may remain in the circuit arrangement.
摘要翻译：一种用于制造包含电容器的集成电路装置的方法。借助于两层蚀刻工艺，借助于硬掩模来构造电介质层。在电绝缘硬掩模的情况下，再次去除硬掩模。在导电硬掩模的情况下，硬掩模的部分可能保留在电路装置中。

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