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11. 发明授权

US6066574A Hot plate cure process for BCB low k interlevel dielectric 有权
标题翻译： BCB低k层间电介质的热板固化工艺
公开(公告)号：US6066574A
公开(公告)日：2000-05-23
申请号：US187429
申请日：1998-11-06
申请人： Lu You , Dawn Hopper , Christof Streck
发明人： Lu You , Dawn Hopper , Christof Streck
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/768 , H01L21/31
CPC分类号： H01L21/31058 , H01L21/312
摘要： A dielectric layer comprising a benzocyclobutene (BCB)-based low dielectric constant (low k) material is formed on a surface of a semiconductor wafer substrate by (a) spin coating a layer of a fluid material comprising BCB in a liquid solvent or dispersant vehicle on the substrate; (b) baking the coated substrate at a first temperature and for a first time interval to remove the solvent; (c) curing the baked coating by heating at a second temperature higher than the first temperature, and for a second time interval; and (d) subjecting the substrate with cured coating thereon to a cool-down treatment at a third temperature and for a third time interval. Embodiments include performing steps (a)-(d) consecutively and in the same apparatus. Other embodiments include processing in an "on track" type automated semiconductor processing apparatus.
摘要翻译：通过以下步骤，在半导体晶片衬底的表面上形成包含基于苯并环丁烯（BCB）的低介电常数（低k）材料的电介质层：（a）在液体溶剂或分散剂载体中旋涂包含BCB的流体材料层在基材上（b）在第一温度和第一时间间隔烘烤涂覆的基材以除去溶剂; （c）通过在高于第一温度的第二温度下加热固化烘烤的涂层，并且持续第二时间间隔; 和（d）在其上固化的涂层对基板进行第三温度和第三时间间隔的冷却处理。实施例包括在相同的装置中连续执行步骤（a） - （d）。其他实施例包括在“轨道”型自动半导体处理装置中的处理。

12. 发明授权

US08202810B2 Low-H plasma treatment with N2 anneal for electronic memory devices 有权
标题翻译：用于电子存储器件的N 2退火的低-H等离子体处理
公开(公告)号：US08202810B2
公开(公告)日：2012-06-19
申请号：US11971331
申请日：2008-01-09
申请人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
发明人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
IPC分类号： H01L21/31
CPC分类号： H01L21/76877 , H01L21/76814 , H01L21/76828 , H01L21/76834 , H01L21/76883 , Y10S438/902
摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.
摘要翻译：一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

13. 发明申请

US20080108193A1 Cu annealing for improved data retention in flash memory devices 有权
标题翻译： Cu退火以改善闪存器件中的数据保留
公开(公告)号：US20080108193A1
公开(公告)日：2008-05-08
申请号：US11593086
申请日：2006-11-06
申请人： Lu You , Alexander Nickel , Minh Q. Tran , Minh-Van Ngo , Hieu Pham , Erik Wilson , Hirokazu Tokuno , Amir Hossein Jafarpour , Inkuk Kang , Robert Huertas
发明人： Lu You , Alexander Nickel , Minh Q. Tran , Minh-Van Ngo , Hieu Pham , Erik Wilson , Hirokazu Tokuno , Amir Hossein Jafarpour , Inkuk Kang , Robert Huertas
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/76883 , H01L27/11521
摘要： Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.
摘要翻译：通过减少后端处理中的氢离子的产生和/或扩散（例如退火的Cu）来改善闪存器件（例如镜像位装置）中的数据保留。实施方案包括在含有低H 2 N 2或无H 2 N的N 2 O 2气氛中以及在低于200℃的温度下退火嵌入的Cu，例如，100℃至150℃

14. 发明申请

US20080096364A1 Conformal liner for gap-filling 审中-公开
标题翻译：用于间隙填充的保形衬套
公开(公告)号：US20080096364A1
公开(公告)日：2008-04-24
申请号：US11582442
申请日：2006-10-18
申请人： Erik Wilson , Minh-Van Ngo , Hieu Pham , Robert Huertas , Lu You , Hirokazu Tokuno , Alexander Nickel , Minh Tran
发明人： Erik Wilson , Minh-Van Ngo , Hieu Pham , Robert Huertas , Lu You , Hirokazu Tokuno , Alexander Nickel , Minh Tran
IPC分类号： H01L21/76
CPC分类号： H01L21/823468 , H01L21/76829 , H01L21/76837 , H01L21/823437
摘要： Gap filling between features which are closely spaced is significantly improved by initially depositing a thin conformal layer followed by depositing a layer of gap filling dielectric material. Embodiments include depositing a thin conformal layer of silicon nitride or silicon oxide, as by atomic layer deposition or pulsed layer deposition, into the gap between adjacent gate electrode structures such that it flows into undercut regions of dielectric spacers on side surfaces of the gate electrode structures, and then depositing a layer of BPSG or P-HDP oxide on the thin conformal layer into the gap. Embodiments further include depositing the layers at a temperature less than 430° C., as by depositing a P-HDP oxide after depositing the conformal liner when the gate electrode structures include a layer of nickel silicide.
摘要翻译：通过初始沉积薄的共形层，然后沉积一层间隙填充电介质材料，密切间隔的特征之间的间隙填充显着改善。实施例包括通过原子层沉积或脉冲层沉积将氮化硅或氧化硅的薄保形层沉积到相邻栅电极结构之间的间隙中，使得其流到栅电极结构的侧表面上的电介质间隔物的底切区域，然后在薄的共形层上沉积一层BPSG或P-HDP氧化物到间隙中。实施例还包括在低于430℃的温度下沉积层，如通过在栅极电极结构包括硅化镍层沉积保形衬垫之后沉积P-HDP氧化物。

15. 发明授权

US07309650B1 Memory device having a nanocrystal charge storage region and method 有权
标题翻译：具有纳米晶体电荷存储区域和方法的存储器件
公开(公告)号：US07309650B1
公开(公告)日：2007-12-18
申请号：US11065388
申请日：2005-02-24
申请人： Connie Pin-Chin Wang , Lu You , Zoran Krivokapic , Paul Raymond Besser , Suzette Keefe Pangrle
发明人： Connie Pin-Chin Wang , Lu You , Zoran Krivokapic , Paul Raymond Besser , Suzette Keefe Pangrle
IPC分类号： H01L21/44
CPC分类号： H01L29/7833 , B82Y10/00 , H01L21/28273 , H01L29/42332
摘要： A memory device having a metal nanocrystal charge storage structure and a method for its manufacture. The memory device may be manufactured by forming a first oxide layer on the semiconductor substrate, then disposing a porous dielectric layer on the oxide layer and disposing a second oxide layer on the porous dielectric layer. A layer of electrically conductive material is formed on the second layer of dielectric material. An etch mask is formed on the electrically conductive material. The electrically conductive material and the underlying dielectric layers are anisotropically etched to form a dielectric structure on which a gate electrode is disposed. A metal layer is formed on the dielectric structure and the gate electrode and treated so that portions of the metal layer diffuse into the porous dielectric layer. Then the metal layer is removed.
摘要翻译：一种具有金属纳米晶体电荷存储结构的存储器件及其制造方法。存储器件可以通过在半导体衬底上形成第一氧化物层，然后在氧化物层上设置多孔介电层并在第二氧化物层上设置第二氧化物层来制造。在第二介电材料层上形成一层导电材料。在导电材料上形成蚀刻掩模。导电材料和下面的介电层被各向异性地蚀刻以形成其上设置有栅电极的电介质结构。在介电结构和栅电极上形成金属层，并处理金属层的一部分扩散到多孔介电层中。然后去除金属层。

16. 发明申请

US20050085073A1 Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition 失效
标题翻译：使用化学气相沉积（CVD）铜沉积的粘附前体层的方法
公开(公告)号：US20050085073A1
公开(公告)日：2005-04-21
申请号：US10687186
申请日：2003-10-16
申请人： Sergey Lopatin , Paul Besser , Alline Myers , Jeremias Romero , Minh Tran , Lu You , Connie Wang
发明人： Sergey Lopatin , Paul Besser , Alline Myers , Jeremias Romero , Minh Tran , Lu You , Connie Wang
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76846 , H01L21/76877
摘要： An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.
摘要翻译：示例性实施例涉及在集成电路制造工艺中使用粘附前体的方法。该方法包括在介电材料上提供材料的气体并在粘附前体层上提供铜层。粘附前体层由气体形成，电介质材料包括孔。

17. 发明授权

US06699792B1 Polymer spacers for creating small geometry space and method of manufacture thereof 有权
标题翻译：用于产生小几何空间的聚合物间隔物及其制造方法
公开(公告)号：US06699792B1
公开(公告)日：2004-03-02
申请号：US09907398
申请日：2001-07-17
申请人： Fei Wang , Lu You , Lynne Okada
发明人： Fei Wang , Lu You , Lynne Okada
IPC分类号： H01L21311
CPC分类号： H01L21/32139 , H01L21/0271 , H01L21/0338 , H01L21/31144
摘要： In forming an opening or space in a substrate, a layer of photoresist is provided on the substrate, and the photoresist is patterned to provide photoresist bodies having respective adjacent sidewalls. A polymer layer is provided on the resulting structure through a low temperature conformal CVD process. The polymer layer is anisotropically etched to form spacers on the respective adjacent sidewalls of the photoresist bodies. The substrate is then etched using the spacers as a mask.
摘要翻译：在形成衬底中的开口或空间时，在衬底上提供光致抗蚀剂层，并且对光致抗蚀剂进行图案化以提供具有相应相邻侧壁的光致抗蚀剂体。通过低温保形CVD工艺在所得结构上提供聚合物层。聚合物层被各向异性蚀刻以在光致抗蚀剂体的各个相邻侧壁上形成间隔物。然后使用间隔物作为掩模蚀刻衬底。

18. 发明授权

US06635943B1 Method and system for reducing charge gain and charge loss in interlayer dielectric formation 有权
标题翻译：降低层间电介质形成中电荷增益和电荷损失的方法和系统
公开(公告)号：US06635943B1
公开(公告)日：2003-10-21
申请号：US09533617
申请日：2000-03-22
申请人： Angela T. Hui , Tuan Duc Pham , Richard J. Huang , Mark T. Ramsbey , Lu You
发明人： Angela T. Hui , Tuan Duc Pham , Richard J. Huang , Mark T. Ramsbey , Lu You
IPC分类号： H01L2900
CPC分类号： H01L21/823425 , H01L21/76819 , H01L21/76837
摘要： A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The interlayer dielectric is capable of gap filling while using only species of relatively low mobility. The method and system also include planarizing a surface of the interlayer dielectric.
摘要翻译：公开了一种用于将半导体器件的下层与半导体器件的上层绝缘的方法和系统。该方法和系统包括在下层上提供层间电介质。层间电介质能够间隙填充，同时仅使用相对较低迁移率的物质。该方法和系统还包括平坦化层间电介质的表面。

19. 发明授权

US06518167B1 Method of forming a metal or metal nitride interface layer between silicon nitride and copper 有权
标题翻译：在氮化硅和铜之间形成金属或金属氮化物界面层的方法
公开(公告)号：US06518167B1
公开(公告)日：2003-02-11
申请号：US10123588
申请日：2002-04-16
申请人： Lu You , Matthew S. Buynoski , Paul R. Besser , Jeremias D. Romero , Pin-Chin Connie Wang , Minh Q. Tran
发明人： Lu You , Matthew S. Buynoski , Paul R. Besser , Jeremias D. Romero , Pin-Chin Connie Wang , Minh Q. Tran
IPC分类号： H01L214763
CPC分类号： H01L21/76849 , H01L21/28562 , H01L21/76834
摘要： A method of forming a metal or metal nitride layer interface between a copper layer and a silicon nitride layer can include providing a metal organic gas or metal/metal nitride precursor over a copper layer, forming a metal or metal nitride layer from reactions between the metal organic gas or metal/metal nitride precursor and the copper layer, and depositing a silicon nitride layer over the metal or metal nitride layer and copper layer. The metal or metal nitride layer can provide a better interface adhesion between the silicon nitride layer and the copper layer. The metal layer can improve the interface between the copper layer and the silicon nitride layer, improving electromigration reliability and, thus, integrated circuit device performance.
摘要翻译：在铜层和氮化硅层之间形成金属或金属氮化物层界面的方法可以包括在铜层上提供金属有机气体或金属/金属氮化物前体，从金属或金属氮化物层之间的反应形成金属或金属氮化物层有机气体或金属/金属氮化物前体和铜层，以及在金属或金属氮化物层和铜层上沉积氮化硅层。金属或金属氮化物层可以在氮化硅层和铜层之间提供更好的界面粘合性。金属层可以改善铜层和氮化硅层之间的界面，提高电迁移可靠性，从而提高集成电路器件的性能。

20. 发明授权

US06420278B1 Method for improving the dielectric constant of silicon-based semiconductor materials 失效
标题翻译：改善硅基半导体材料介电常数的方法
公开(公告)号：US06420278B1
公开(公告)日：2002-07-16
申请号：US09096760
申请日：1998-06-12
申请人： Dawn M. Hopper , Richard J. Huang , Lu You
发明人： Dawn M. Hopper , Richard J. Huang , Lu You
IPC分类号： H01L2131
CPC分类号： H01L21/02134 , H01L21/02282 , H01L21/3124
摘要： An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials in which the dielectric constant has been reduced by spinning on the dielectric to silicon wafers, eliminating soft bake steps, and heating the wafers to about 400° C. for about one hour in a vacuum or inert atmosphere.
摘要翻译：通过使用硅基低介电常数材料制造超大规模集成电路，其中介电常数通过在电介质上旋转至硅晶片而减少，消除了软烘烤步骤，并将晶片加热至约400℃ 在真空或惰性气氛中约1小时。

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