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11. 发明授权

US06754781B2 Cache with DMA and dirty bits 有权
标题翻译：缓存与DMA和脏位
公开(公告)号：US06754781B2
公开(公告)日：2004-06-22
申请号：US09932643
申请日：2001-08-17
申请人： Gerard Chauvel , Serge Lasserre
发明人： Gerard Chauvel , Serge Lasserre
IPC分类号： G06F1208
CPC分类号： G06F9/30043 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F12/0292 , G06F12/0804 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (506(n). Validity circuitry (VI) is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Dirty bit circuitry (DI) is connected to the memory circuit for indicating if data within the cache is incoherent with a secondary back-up memory. DMA circuitry can transfer (1652) blocks of data/instructions (1660) between the cache and a secondary memory (1602). A transfer mode circuit (1681) controls how DMA operations are affected by the dirty bits. If the transfer mode circuit is in a first mode, a DMA operation transfers only segments (1661) indicated as dirty (1685). If the transfer mode circuit is in a second mode, a DMA operation transfers and entire block of data (1660) without regard to dirty indicators (1686). DMA transfers from the cache to secondary memory are thereby configured to be responsive to the dirty bits. A dirty bit mode circuit (1680) controls how DMA transfers affect the dirty bits. When the mode circuit is in a first mode, DMA transfers set the affected dirty bits to a clean state. When the dirty bit mode circuitry is in an alternate mode, DMA transfers set the affected dirty bits to a dirty state. A cache clean operation will thus copy data provided by a DMA transfer and indicated as dirty into backup secondary memory.
摘要翻译：提供了一种数字系统和操作方法，其中数字系统具有至少一个具有相关联的多段高速缓冲存储器电路（506（n））的处理器，有效电路（VI）连接到存储器电路，并且可操作以指示多个段的每个段是否保存有效数据，脏位电路（DI）连接到存储器电路，用于指示高速缓存内的数据是否与辅助备份存储器不相干，DMA电路可以传输（1652）块传输模式电路（1681）控制DMA操作如何受脏位的影响，如果传输模式电路处于第一模式，DMA操作（1660）只传输指示为脏的段（1661）（1685），如果传输模式电路处于第二模式，则DMA操作传输和整个数据块（1660），而不考虑脏指示器（1686）。到二级记忆从而被配置为响应于脏位。脏位模式电路（1680）控制DMA传输如何影响脏位。当模式电路处于第一模式时，DMA将受影响的脏位设置为干净状态。当脏位模式电路处于交替模式时，DMA传送将受影响的脏位设置为脏状态。因此，高速缓存清理操作将复制由DMA传输提供的数据，并将其标记为脏到备用辅助存储器中。

12. 发明授权

US06728838B2 Cache operation based on range of addresses 有权
标题翻译：基于地址范围的缓存操作
公开(公告)号：US06728838B2
公开(公告)日：2004-04-27
申请号：US09932634
申请日：2001-08-17
申请人： Gerard Chauvel , Serge Lasserre
发明人： Gerard Chauvel , Serge Lasserre
IPC分类号： G06F1212
CPC分类号： G06F1/329 , G06F1/206 , G06F1/3203 , G06F9/30047 , G06F12/0292 , G06F12/0804 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (1806(n). Validity circuitry (VI) and dirty bit circuitry (DI) is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Block circuitry (700, 702) is connected to the set of valid bits and dirty bits and is operable to invalidate a selected range of lines in response to a directive from the first processor. The block circuitry has a start register (700) and an end register (702) each separately loadable by the processor. The block circuitry can invalidate either a single line or a block of lines in response to an operation command from the processor, depending on whether the end register is loaded or not. Likewise, the block circuitry can clean a single line or a block of lines in response to an operation command from the processor.
摘要翻译：提供了一种数字系统和操作方法，其中数字系统具有至少一个处理器，具有相关联的多段高速缓冲存储器电路（1806（n）），有效电路（VI）和脏位电路（DI）连接到存储器电路并且可操作以指示多个段中的每个段是否保存有效数据。块电路（700,702）连接到该组有效位和脏位，并且可操作以使响应中的所选行范围无效块电路具有开始寄存器（700）和结束寄存器（702），每个开关寄存器（700）和终端寄存器（702）都可以由处理器分别加载。块电路可以响应于第一处理器使单行或一组线路无效来自处理器的操作命令，取决于结束寄存器是否被加载。同样地，块电路可以响应于来自处理器的操作命令来清除单行或一行线。

13. 发明授权

US06310657B1 Real time window address calculation for on-screen display 有权
标题翻译：屏幕显示实时窗口地址计算
公开(公告)号：US06310657B1
公开(公告)日：2001-10-30
申请号：US09679000
申请日：2000-10-04
申请人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
发明人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
IPC分类号： H04N550
CPC分类号： H04N21/8166 , G09G5/14 , G09G5/395 , G09G2340/04 , G09G2340/125 , G09G2360/02 , H04L29/06 , H04L69/22 , H04N5/44 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N7/0882 , H04N11/20 , H04N19/42 , H04N19/61 , H04N21/42204 , H04N21/426 , H04N21/42615 , H04N21/42623 , H04N21/42653 , H04N21/4305 , H04N21/431 , H04N21/4316 , H04N21/434 , H04N21/43632 , H04N21/439 , H04N21/44 , H04N21/443 , H04N21/47
摘要： An on-screen display system in which a CPU generates windows in a working memory space also provides for real time calculation of window addresses in the working memory space. This can eliminate the need for a separate frame buffer memory.
摘要翻译：其中CPU在工作存储器空间中生成窗口的屏幕显示系统还提供对工作存储器空间中的窗口地址的实时计算。这可以消除对单独的帧缓冲存储器的需要。

14. 发明授权

US08429383B2 Multi-processor computing system having a JAVA stack machine and a RISC-based processor 有权
标题翻译：具有JAVA堆栈机和基于RISC处理器的多处理器计算系统
公开(公告)号：US08429383B2
公开(公告)日：2013-04-23
申请号：US10631939
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Maija Kuusela , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Maija Kuusela , Dominique D'Inverno
IPC分类号： G06F15/76
CPC分类号： G06F12/0253 , G06F9/30101 , G06F9/30174 , G06F9/3879 , G06F12/0804 , G06F12/0875 , G06F12/0891 , G06F12/1036 , G06F12/126 , G06F2212/502 , G06F2212/681
摘要： A system comprises a first processor, a second processor coupled to the first processor, memory coupled to, and shared by, the first and second processors, and a synchronization unit coupled to the first and second processors. The second processor preferably comprises stack storage that resides in the core of the second processor. Further, the second processor executes stack-based instructions while the first processor executes one or more tasks including, for example, managing the memory via an operating system that executes only on the first processor. Associated methods are also disclosed.
摘要翻译：系统包括第一处理器，耦合到第一处理器的第二处理器，耦合到第一和第二处理器并由其共享的存储器，以及耦合到第一和第二处理器的同步单元。第二处理器优选地包括位于第二处理器的核心中的堆栈存储器。此外，第二处理器执行基于堆栈的指令，而第一处理器执行一个或多个任务，包括例如经由只在第一处理器上执行的操作系统来管理存储器。还公开了相关方法。

15. 发明授权

US07565385B2 Embedded garbage collection 有权
标题翻译：嵌入式垃圾收集
公开(公告)号：US07565385B2
公开(公告)日：2009-07-21
申请号：US10831387
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F17/00
CPC分类号： G06F12/0269 , Y02D10/13 , Y10S707/99957
摘要： An electronic system comprises a processor, memory coupled to the processor, and an application programming interface that causes an embedded garbage collection object to be active. The memory stores one or more objects that selectively have references from root objects. The embedded garbage collection object preferably uses control data to cause objects to be removed from said memory, the removed objects comprise those objects that were created while an embedded garbage collection object was active and that do not have references from root objects.
摘要翻译：电子系统包括处理器，耦合到处理器的存储器以及使嵌入式垃圾回收对象活动的应用编程接口。存储器存储一个或多个选择性地具有来自根对象的引用的对象。嵌入式垃圾回收对象优选地使用控制数据来使对象从所述存储器中移除，所移除的对象包括当嵌入式垃圾回收对象是活动的并且没有来自根对象的引用时创建的对象。

16. 发明授权

US07434021B2 Memory allocation in a multi-processor system 有权
标题翻译：多处理器系统中的内存分配
公开(公告)号：US07434021B2
公开(公告)日：2008-10-07
申请号：US10831388
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F9/5016 , Y02D10/22
摘要： A process and associated system comprise pre-allocating a portion of memory in a first processor based upon a control input and determining in a second processor if the portion of the pre-allocated memory can satisfy a memory allocation request. Further, if a portion of pre-allocated memory can satisfy a memory allocation request, the technique includes assigning the pre-allocated portion of memory to the allocation request. However, if a portion of pre-allocated memory cannot satisfy a memory allocation request, the technique includes allocating a portion of memory in the first processor to the allocation request.
摘要翻译：过程和相关系统包括基于控制输入在第一处理器中预分配存储器的一部分，并且在第二处理器中确定预分配存储器的部分是否可以满足存储器分配请求。此外，如果预先分配的存储器的一部分可以满足存储器分配请求，则该技术包括将存储器的预分配部分分配给分配请求。然而，如果预分配存储器的一部分不能满足存储器分配请求，则该技术包括将第一处理器中的存储器的一部分分配给分配请求。

17. 发明授权

US07386671B2 Smart cache 有权
标题翻译：智能缓存
公开(公告)号：US07386671B2
公开(公告)日：2008-06-10
申请号：US10891821
申请日：2004-07-14
申请人： Gerard Chauvel , Serge Lasserre , Dominique Benoit Jacques D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Dominique Benoit Jacques D'Inverno
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F12/0864
摘要： A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20). The hit/miss logic (46) also determines whether a line should be loaded into the RAM set data array (38) or in the associated cache.
摘要翻译：用于处理设备的高速缓存结构（16）包括用于缓存主存储器（20）的连续块的RAM组高速缓存。 RAM集缓存可以与其他缓存类型一起使用，例如集合关联高速缓存或直接映射高速缓存。寄存器（32）定义主存储器（20）的连续块的起始地址。与RAM组相关联的数据阵列（38）可以逐行填充，因为处理核心请求线路，或者在开始时填充数据阵列（38）的设置填充基础上地址被加载到寄存器（32）中。由于从处理核心接收到地址，因此使用命中/未命中逻辑（46）起始地址寄存器（32），全局有效位（34），行有效位（37）和控制位（24,26）来确定数据是否存在于RAM集合中，或者数据是否必须从主存储器（20）加载。命中/未命中逻辑（46）还确定是否将线路加载到RAM集数据阵列（38）或相关联的高速缓存中。

18. 发明授权

US06996683B2 Cache coherency in a multi-processor system 有权
标题翻译：多处理器系统中的高速缓存一致性
公开(公告)号：US06996683B2
公开(公告)日：2006-02-07
申请号：US10632229
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Maija Kuusela , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Maija Kuusela , Dominique D'Inverno
IPC分类号： G06F12/02
CPC分类号： G06F9/30134 , G06F9/30101 , G06F9/30174 , G06F9/3834 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A system comprises a first processor having cache memory, a second processor having cache memory and a coherence buffer that can be enabled and disabled by the first processor. The system also comprises a memory subsystem coupled to the first and second processors. For a write transaction originating from the first processor, the first processor enables the second processor's coherence buffer, and information associated with the first processor's write transaction is stored in the second processor's coherence buffer to maintain data coherency between the first and second processors.
摘要翻译：一种系统包括具有高速缓冲存储器的第一处理器，具有高速缓冲存储器的第二处理器和可由第一处理器启用和禁用的相干缓冲器。该系统还包括耦合到第一和第二处理器的存储器子系统。对于来自第一处理器的写入事务，第一处理器启用第二处理器的相干缓冲器，并且与第一处理器的写入事务相关联的信息被存储在第二处理器的相干缓冲器中以维持第一和第二处理器之间的数据一致性。

19. 发明授权

US06851072B2 Fault management and recovery based on task-ID 有权
标题翻译：基于任务ID的故障管理和恢复
公开(公告)号：US06851072B2
公开(公告)日：2005-02-01
申请号：US09932378
申请日：2001-08-17
申请人： Serge Lasserre , Gerard Chauvel
发明人： Serge Lasserre , Gerard Chauvel
IPC分类号： G06F1/20 , G06F1/32 , G06F9/312 , G06F9/50 , G06F11/07 , G06F11/20 , G06F11/34 , G06F12/02 , G06F12/08 , G06F12/10
CPC分类号： G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30043 , G06F11/0715 , G06F11/0772 , G06F11/0793 , G06F11/1666 , G06F11/20 , G06F12/0292 , G06F12/0879 , G06F12/0891 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , G06F2212/681 , Y02D10/13 , Y02D10/24
摘要： In accordance with a first embodiment of the invention, there is provided a method of operating a digital system that has a processor and a memory. A plurality of program tasks is executed on the processor (800). The processor requests access to memory in response to executing the tasks (802). Some of these access requests are not directly or not straightforwardly linked with the current program counter (PC); for example, a write transaction going through a write buffer (808). An access error resulting form this type of transaction error is referred to as an imprecise abort. A task-id value is supplied along with the address during a deferred memory access and corresponds to the task-id of the task that initiated the memory access (802). If an error condition that prevents normal completion of the memory transaction is detected (806), then a recovery routine uses the task-id value provided with the memory transaction request to identify which program task requested the transaction (810, 812). The recovery routine can then resolve the problem or kill the identified task.
摘要翻译：根据本发明的第一实施例，提供了一种操作具有处理器和存储器的数字系统的方法。在处理器（800）上执行多个程序任务。响应于执行任务，处理器请求访问存储器（802）。这些访问请求中的一些不直接或不直接与当前的程序计数器（PC）链接; 例如，通过写入缓冲器的写入事务（808）。这种类型的事务错误导致的访问错误被称为不精确中止。任务ID值与延迟存储器访问期间的地址一起提供，并且对应于启动存储器访问的任务的任务ID（802）。如果检测到存储器事务的正常完成的错误条件（806），则恢复例程使用与存储器事务请求一起提供的task-id值来识别请求事务的程序任务（810,812）。然后，恢复例程可以解决问题或者杀死已识别的任务。

20. 发明授权

US06697916B2 Cache with block prefetch and DMA 有权
标题翻译：缓存带块预取和DMA
公开(公告)号：US06697916B2
公开(公告)日：2004-02-24
申请号：US09932650
申请日：2001-08-17
申请人： Serge Lasserre , Gerard Chauvel
发明人： Serge Lasserre , Gerard Chauvel
IPC分类号： G06F1206
CPC分类号： G06F9/30043 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F12/0292 , G06F12/0835 , G06F12/0862 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (506(n). Validity circuitry (VI) is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Block transfer circuitry (700, 702) is connected to the memory circuit and is operable to transfer a block of data (1650) to a selected portion of segments (1606) of the cache memory circuit. Fetch circuitry associated with the memory cache is operable to transfer data from a pre-selected region of the secondary memory (1650) to a particular segment of the plurality of segments and to assert a first valid bit corresponding to the segment when the miss detection circuitry (1610) detects a miss in the segment. Direct memory access (DMA) circuitry (1610) is connected to the memory cache for transferring data between the memory cache and a selectable region (1650) of a secondary memory. The cache can be operated in a first manner such that when a transfer request from the processor requests a first location in the cache memory that does not hold valid data, valid data is transferred (1652) from a pre-selected location in a secondary memory that corresponds directly to the first location. The cache can then be operated in a second manner such that data is transferred (1662) between the first location and a selectable location in the secondary memory, wherein the selected location need not directly correspond to the first location.
摘要翻译：提供了一种数字系统和操作方法，其中数字系统具有至少一个具有相关联的多段高速缓冲存储器电路（506（n））的处理器，有效电路（VI）连接到存储器电路，并且可操作以块传输电路（700,702）连接到存储器电路，并且可操作以将数据块（1650）传送到所述多个段的片段（1606）的选定部分与存储器高速缓存相关联的获取电路可操作以将数据从辅助存储器（1650）的预先选择的区域传送到多个段的特定段，并且当对应于该段的第一有效位时未命中检测电路（1610）检测该片段中的未命中，直接存储器访问（DMA）电路（1610）连接到存储器高速缓存，用于在存储器高速缓存和可选区域（1650）之间传送数据第一记忆高速缓存可以以第一方式操作，使得当来自处理器的传送请求请求高速缓冲存储器中不保存有效数据的第一位置时，有效数据从副存储器中的预先选择的位置传送（1652）它直接对应于第一个位置。然后可以以第二方式操作高速缓存，使得数据在辅助存储器中的第一位置和可选位置之间传送（1662），其中所选择的位置不需要直接对应于第一位置。

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