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1. 发明授权

US07757067B2 Pre-decoding bytecode prefixes selectively incrementing stack machine program counter 有权
标题翻译：预解码字节码前缀选择性地递增堆栈机器程序计数器
公开(公告)号：US07757067B2
公开(公告)日：2010-07-13
申请号：US10632222
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Maija Kuusela
发明人： Gerard Chauvel , Serge Lasserre , Maija Kuusela
IPC分类号： G06F9/30 , G06F9/40
CPC分类号： G06F9/30149 , G06F9/30076 , G06F9/30181 , G06F9/30185 , G06F9/382 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A processor (e.g., a co-processor) comprising a decoder coupled to a pre-decoder, in which the decoder decodes a current instruction in parallel with the pre-decoder pre-decoding a subsequent instruction. In particular, the pre-decoder examines at least five Bytecodes in parallel with the decoder decoding a current instruction. The pre-decoder determines if a subsequent instruction contains a prefix. If a prefix is detected in at least one of the five Bytecodes, a program counter skips the prefix and changes the behavior of the decoder during the decoding of the subsequent instruction.
摘要翻译：包括耦合到预解码器的解码器的处理器（例如，协处理器），其中解码器与预解码器并行地解码当前指令，以对后续指令进行解码。特别地，预解码器与解码器解码当前指令并行地检查至少五个字节码。预解码器确定后续指令是否包含前缀。如果在五个字节码中的至少一个中检测到前缀，则程序计数器跳过前缀，并且在后续指令的解码期间改变解码器的行为。

2. 发明授权

US07496930B2 Accessing device driver memory in programming language representation 有权
标题翻译：以编程语言表示访问设备驱动程序内存
公开(公告)号：US07496930B2
公开(公告)日：2009-02-24
申请号：US10831575
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F13/00
CPC分类号： G09G5/39 , G06F3/14 , G09G5/393
摘要： In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application software comprises instructions that initialize an application data structure (e.g., an object or array) usable by the application software to manage the device and also comprises instructions that map the application data structure to a memory associated with the device without the use of a device driver. In other embodiments, a method comprises initializing an application data structure to manage a hardware device and mapping the application data structure to a memory associated with the hardware device without the use of a device driver. The application data structure may store a single dimensional data structure or a multi-dimensional data structure. In some embodiments, the device being managed by the application software may comprise a display and the application software may comprise Java code.
摘要翻译：在一些实施例中，存储介质包括执行一个或多个操作并直接管理设备的应用软件。应用软件包括初始化应用软件可用于管理设备的应用数据结构（例如，对象或阵列）的指令，还包括将应用数据结构映射到与设备相关联的存储器而不使用设备驱动。在其他实施例中，一种方法包括初始化应用数据结构以管理硬件设备，并将应用数据结构映射到与硬件设备相关联的存储器，而不使用设备驱动程序。应用数据结构可以存储单维数据结构或多维数据结构。在一些实施例中，由应用软件管理的设备可以包括显示器，并且应用软件可以包括Java代码。

3. 发明申请

US20050033945A1 Dynamically changing the semantic of an instruction 审中-公开
标题翻译：动态地改变指令的语义
公开(公告)号：US20050033945A1
公开(公告)日：2005-02-10
申请号：US10830917
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banatre , Jean-Paul Routeau , Salam Majoul , Frederic Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banatre , Jean-Paul Routeau , Salam Majoul , Frederic Parain
IPC分类号： G06F9/22 , G06F9/318 , G06F9/44 , G06F11/34 , G06F12/00 , G06F9/30
CPC分类号： G06F11/3466 , G06F9/30087 , G06F9/30174 , G06F9/30189 , G06F2201/865 , G06F2201/88
摘要： A technique comprises receiving an instruction and dynamically changing the instruction's semantic based on programmable information that is separate from the instruction. The change in semantic may comprise the inclusion of monitoring code that determines a performance characteristic associated with the instruction or a change in the instruction's operation (e.g., the inclusion of read or write barrier operations to support a garbage collector).
摘要翻译：一种技术包括接收指令并基于与指令分离的可编程信息来动态地改变指令的语义。语义的变化可以包括包括确定与指令相关联的性能特征的监视代码或指令的操作的改变（例如，包括用于支持垃圾收集器的读取或写入屏障操作）。

4. 发明授权

US06826652B1 Smart cache 有权
标题翻译：智能缓存
公开(公告)号：US06826652B1
公开(公告)日：2004-11-30
申请号：US09591537
申请日：2000-06-09
申请人： Gerard Chauvel , Serge Lasserre , Dominique Benoit Jacques D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Dominique Benoit Jacques D'Inverno
IPC分类号： G06F1208
CPC分类号： G06F12/0897 , G06F2212/2515
摘要： A cache architecture (16) for use in a processing includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20). The hit/miss logic (46) also determines whether a line should be loaded into the RAM set data array (38) or in the associated cache.
摘要翻译：用于处理的缓存结构（16）包括用于缓存主存储器（20）的连续块的RAM集缓存。 RAM集缓存可以与其他缓存类型一起使用，例如集合关联高速缓存或直接映射高速缓存。寄存器（32）定义主存储器（20）的连续块的起始地址。与RAM组相关联的数据阵列（38）可以逐行填充，因为处理核心请求线路，或者在开始时填充数据阵列（38）的设置填充基础上地址被加载到寄存器（32）中。由于从处理核心接收到地址，因此使用命中/未命中逻辑（46）起始地址寄存器（32），全局有效位（34），行有效位（37）和控制位（24,26）来确定数据是否存在于RAM集合中，或者数据是否必须从主存储器（20）加载。命中/未命中逻辑（46）还确定是否将线路加载到RAM集数据阵列（38）或相关联的高速缓存中。

5. 发明授权

US06751706B2 Multiple microprocessors with a shared cache 有权
标题翻译：具有共享缓存的多个微处理器
公开(公告)号：US06751706B2
公开(公告)日：2004-06-15
申请号：US09932651
申请日：2001-08-17
申请人： Gerard Chauvel , Maija Kuusela , Dominique D'Inverno , Serge Lasserre
发明人： Gerard Chauvel , Maija Kuusela , Dominique D'Inverno , Serge Lasserre
IPC分类号： G06F1200
CPC分类号： G06F9/5011 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30043 , G06F9/5094 , G06F11/3409 , G06F12/0292 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/815 , G06F2201/86 , G06F2201/88 , G06F2201/885 , G06F2209/5014 , G06F2209/5021 , G06F2209/507 , G06F2212/1028 , G06F2212/681 , Y02D10/13 , Y02D10/16 , Y02D10/22 , Y02D10/24 , Y02D10/34
摘要： A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. When the L2-cache misses, the penalty to access to data within the L3 memory is high. The system supports miss under miss to let a second miss interrupt a segment prefetch being done in response to a first miss. Thus, an interruptible SDRAM to L2-cache prefetch system with miss under miss support is provided. A shared translation look-aside buffer (TLB) is provided for L2 accesses, while a private TLB is associated with each processor. A micro TLB (&mgr;TLB) is associated with each resource that can initiate a memory transfer. The L2 cache, along with all of the TLBs and &mgr;TLBs have resource ID fields and task ID fields associated with each entry to allow flushing and cleaning based on resource or task. Configuration circuitry is provided to allow the digital system to be configured on a task by task basis in order to reduce power consumption.
摘要翻译：数字系统具有几个处理器，与每个处理器相关联的私有一级（L1）高速缓存，每个条目具有多个段的共享二级（L2）高速缓存以及三级（L3）物理存储器。共享的L2高速缓存体系结构体现为4路关联性，每个条目有4个段和4个有效位和脏位。当L2缓存未命中时，访问L3内存中的数据的惩罚很高。该系统支持未命中错过，以使第二个错误中断一个段预取正在响应于第一个错过。因此，提供了一个可中断的SDRAM到L2缓存预取系统，其中错过了支持。为L2访问提供共享翻译后备缓冲器（TLB），而私有TLB与每个处理器相关联。微型TLB（muTLB）与可以启动存储器传输的每个资源相关联。 L2缓存以及所有TLB和muTLB都具有与每个条目关联的资源ID字段和任务ID字段，以允许基于资源或任务的冲洗和清理。提供配置电路以允许数字系统根据任务在任务上进行配置，以便降低功耗。

6. 发明授权

US06745293B2 Level 2 smartcache architecture supporting simultaneous multiprocessor accesses 有权
标题翻译： 2级smartcache架构支持同时多处理器访问
公开(公告)号：US06745293B2
公开(公告)日：2004-06-01
申请号：US09932308
申请日：2001-08-17
申请人： Serge Lasserre , Gerard Chauvel
发明人： Serge Lasserre , Gerard Chauvel
IPC分类号： G06F1200
CPC分类号： G06F9/5011 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30043 , G06F12/084 , G06F12/0846 , G06F12/0879 , G06F12/0891 , G06F2201/81 , G06F2201/885 , G06F2209/5021 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. Multiple detection circuitry responds to several cache access requests concurrently. Multiple ports in the cache service multiple requesters concurrently if concurrent hits are determined by the detection circuitry.
摘要翻译：数字系统具有几个处理器，与每个处理器相关联的私有一级（L1）高速缓存，每个条目具有多个段的共享二级（L2）高速缓存以及三级（L3）物理存储器。共享的L2高速缓存体系结构体现为4路关联性，每个条目有4个段和4个有效位和脏位。多个检测电路同时响应多个缓存访问请求。如果并发命中由检测电路确定，高速缓存服务中的多个端口将同时发送多个请求者。

7. 发明授权

US07840784B2 Test and skip processor instruction having at least one register operand 有权
标题翻译：测试和跳过具有至少一个寄存器操作数的处理器指令
公开(公告)号：US07840784B2
公开(公告)日：2010-11-23
申请号：US10632084
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
IPC分类号： G06F9/32
CPC分类号： G06F9/30069 , G06F9/30181 , G06F9/30185 , G06F9/30189 , G06F9/30196 , G06F9/355 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A processor may execute a test and skip instruction that includes or otherwise specifies at least two operands that are used in a comparison operation. Based on the results of the comparison, the instruction that follows the test and skip instruction is “skipped.” The test and skip instruction may specify that the operands used in the comparison include (1) the contents of two registers, (2) the contents of one register and the contents of a memory location, or (3) the contents of one register and a stack value. In the second mode (an operand being from memory), a register is specified in the test and skip instruction that contains a value from which a pointer may be calculated. The calculated pointer preferably points to the memory location. If a stack value is used in the execution of the test and skip instruction, the instruction may include a reference to a register that points to the top of the stack. Further, the stack pointer may be adjusted automatically if the stack is used to provide an operand for the instruction. Embodiments may include apparatus and methods.
摘要翻译：处理器可以执行包括或以其他方式指定在比较操作中使用的至少两个操作数的测试和跳过指令。根据比较结果，测试和跳过指令之后的指令被“跳过”。测试和跳过指令可以指定比较中使用的操作数包括（1）两个寄存器的内容，（2）一个寄存器的内容和存储器位置的内容，或（3）一个寄存器的内容和堆栈值。在第二模式（一个来自存储器的操作数）中，在测试和跳过指令中指定一个寄存器，该指令包含可以计算指针的值。计算出的指针最好指向存储器位置。如果在执行测试和跳过指令时使用堆栈值，则该指令可以包括对指向堆栈顶部的寄存器的引用。此外，如果堆栈用于为指令提供操作数，则可以自动调整堆栈指针。实施例可以包括装置和方法。

8. 发明授权

US07058765B2 Processor with a split stack 有权
标题翻译：处理器与分离堆栈
公开(公告)号：US07058765B2
公开(公告)日：2006-06-06
申请号：US10632079
申请日：2003-07-31
申请人： Gerard Chauvel , Maija Kuusela , Serge Lasserre
发明人： Gerard Chauvel , Maija Kuusela , Serge Lasserre
IPC分类号： G06F12/08
CPC分类号： G06F9/30134 , G06F9/30101 , G06F9/3012 , G06F9/30174 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0875 , G06F12/0891 , G06F12/1036 , G06F12/126 , G06F2212/502 , G06F2212/681 , Y02D10/13
摘要： Methods and apparatuses are disclosed for implementing a processor with a split stack. In some embodiments, the processor includes a main stack and a micro-stack. The micro-stack preferably is implemented in the core of the processor, whereas the main stack may be implemented in areas that are external to the core of the processor. Operands are preferably provided to an arithmetic logic unit (ALU) by the micro-stack, and in the case of underflow (micro-stack empty), operands may be fetched from the main stack. Operands are written to the main stack during overflow (micro-stack full) or by explicit flushing of the micro-stack. By optimizing the size of the micro-stack, the number of operands fetched from the main stack may be reduced, and consequently the processor's power consumption may be reduced.
摘要翻译：公开了用于实现具有分组堆栈的处理器的方法和装置。在一些实施例中，处理器包括主堆栈和微堆栈。微堆优选地实现在处理器的核心中，而主堆栈可以在处理器核心外部的区域中实现。操作数优选地通过微栈提供给算术逻辑单元（ALU），并且在下溢（微堆空）的情况下，可以从主堆栈获取操作数。在溢出（微型堆栈完整）或通过显式冲洗微型堆栈时，操作数将写入主堆栈。通过优化微堆栈的大小，可以减少从主堆栈取出的操作数的数量，从而可以降低处理器的功耗。

9. 发明授权

US06772326B2 Interruptible an re-entrant cache clean range instruction 有权
标题翻译：中断缓存清除范围指令
公开(公告)号：US06772326B2
公开(公告)日：2004-08-03
申请号：US10157576
申请日：2002-05-29
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
IPC分类号： G06F944
CPC分类号： G06F9/4843 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F12/0842 , G06F12/0891
摘要： A digital system and method of operation is provided in which a method is provided for cleaning a range of addresses in a storage region specified by a start parameter and an end parameter. An interruptible clean instruction (802) can be executed in a sequence of instructions (800) in accordance with a program counter. If an interrupt (804) is received during execution of the clean instruction, execution of the clean instruction is suspended before it is completed. After performing a context switch (810), the interrupt is serviced (820). Upon returning from the interrupt service routine (830, 834), execution of the clean instruction is resumed by comparing the start parameter and the end parameter provided by the clean instruction with a current content of a respective start register and end register used during execution of the clean instruction. If the same, execution of the clean instruction is resumed using the current content of the start register and end register. If different, execution of the clean instruction is restarted by storing the start parameter provided by clean instruction in the start register and by storing the end parameter in the end register. In this manner, no additional context information needs to be saved during a context switch in order to allow the clean instruction to be interruptible. If the interrupt occurred during a non-interruptible instruction, then the instruction is completed before the context switch and a return (830, 832) after the interrupt service routine begins execution at the next instruction (803). Other instructions that perform a sequence of operations can also be made interruptible in a similar manner.
摘要翻译：提供了一种数字系统和操作方法，其中提供了一种用于清洁由起始参数和结束参数指定的存储区域中的地址范围的方法。根据程序计数器，可以以指令序列（800）执行中断清除指令（802）。如果在执行干净指令期间接收到中断（804），干净指令的执行将在完成之前暂停。执行上下文切换（810）后，中断服务（820）。在从中断服务程序（830,834）返回时，通过将清除指令提供的开始参数和结束参数与执行期间使用的相应起始寄存器和结束寄存器的当前内容进行比较来恢复干净指令的执行干净的说明。如果相同，则使用起始寄存器和结束寄存器的当前内容恢复干净指令的执行。如果不同，通过将清除指令提供的启动参数存储在起始寄存器中并通过将结束参数存储在结束寄存器中来重新启动干净指令的执行。以这种方式，在上下文切换期间不需要保存附加上下文信息，以便允许清除指令是可中断的。如果在不可中断指令期间发生中断，则在中断服务程序在下一条指令（803）开始执行之前，上下文切换和返回（830,832）之前完成指令。执行一系列操作的其他指令也可以以类似的方式中断。

10. 发明授权

US06760829B2 MMU descriptor having big/little endian bit to control the transfer data between devices 有权
标题翻译： MMU描述符具有大/小端位以控制设备之间的传输数据
公开(公告)号：US06760829B2
公开(公告)日：2004-07-06
申请号：US09932807
申请日：2001-08-17
申请人： Serge Lasserre , Gerard Chauvel , Dominique D'Inverno
发明人： Serge Lasserre , Gerard Chauvel , Dominique D'Inverno
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F12/0292 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system is provided with a memory (506) shared by several initiator resources (540-550), wherein a portion of the initiator resources are big endian and another portion of the initiator resources are little endian. The memory is segregated into a set of regions by a memory management unit (MMU) (500-510) and an endianism attribute bit is defined for each region. For each memory request to the memory, the endianism attribute bit for the selected region is provided by the MMU. Each memory transaction request is completed in accordance with the endianism attribute of the selected region. Depending on the capability of a given initiator resource, the memory request address is adjusted to agree with the endianism attribute of the selected region, or an access fault is generated (530) if the endianism of the initiating resource does not match the endianism attribute of the selected memory region. A resource identification value (R-ID) provided by each of the initiator resources is used to identify the endianism of each of the initiator resources.
摘要翻译：数字系统具有由几个发起者资源（540-550）共享的存储器（506），其中一部分发起者资源是大端，另一部分发起者资源是小端。存储器通过存储器管理单元（MMU）（500-510）分离成一组区域，并且为每个区域定义一个endianistic属性位。对于存储器的每个存储器请求，MMU提供所选区域的endianistic属性位。每个存储器事务请求都是根据所选区域的endianism属性完成的。根据给定的启动器资源的能力，调整存储器请求地址以与所选区域的endianism属性一致，或者如果启动资源的endianism不匹配于endianism属性，则生成访问故障（530）所选存储区域。由每个启动器资源提供的资源标识值（R-ID）用于识别每个发起者资源的端点。

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