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1. 发明授权

US5644310A Integrated audio decoder system and method of operation 失效
标题翻译：集成音频解码系统及操作方法
公开(公告)号：US5644310A
公开(公告)日：1997-07-01
申请号：US475251
申请日：1995-06-07
申请人： Frank L. Laczko, Sr. , Gerard Benbassat , Kenneth R. Cyr , Stephen H. Li , Shiu Wai Kam , Karen L. Walker , Jonathan L. Rowlands
发明人： Frank L. Laczko, Sr. , Gerard Benbassat , Kenneth R. Cyr , Stephen H. Li , Shiu Wai Kam , Karen L. Walker , Jonathan L. Rowlands
IPC分类号： G06T9/00 , H04B1/66 , H04J3/06 , H03M1/00
CPC分类号： H04B1/665 , G06T9/004 , G06T9/007
摘要： A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).
摘要翻译：公开了一种数据处理系统（10），其包括耦合到解码系统（14）的微处理器主机（12）。主机接口块（18）接收比特流并将比特流传送到系统解码器块（20）。系统解码器块（20）从比特流中提取适当的数据，并加载输入缓冲器（24）或可选的外部缓冲器（26）。音频解码器块（28）从输入缓冲器（24）检索数据，并生成比例因子索引，存储在运算单元缓冲器（30）中的每码字值比特和子带样本。硬件滤波器运算单元块（32）从算术单元缓冲器（30）检索信息，对数据进行去量化，变换和滤波，以产生加载到PCM缓冲器（34）中的PCM输出数据。 PCM缓冲器（34）内的数据由PCM输出块（36）输出到数 - 模转换器（16）。

2. 发明授权

US06452641B1 Method and apparatus for providing and on-screen display with variable resolution capability 有权
标题翻译：用于提供可变分辨能力的屏幕显示的方法和装置
公开(公告)号：US06452641B1
公开(公告)日：2002-09-17
申请号：US09677658
申请日：2000-10-04
申请人： Gerard Chauvel , Gerard Benbassat , Brian O. Chae
发明人： Gerard Chauvel , Gerard Benbassat , Brian O. Chae
IPC分类号： H04N550
CPC分类号： H04N21/8166 , G09G5/14 , G09G5/395 , G09G2340/04 , G09G2340/125 , G09G2360/02 , H04L29/06 , H04L69/22 , H04N5/44 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N7/0882 , H04N11/20 , H04N19/42 , H04N19/61 , H04N21/42204 , H04N21/426 , H04N21/42615 , H04N21/42623 , H04N21/42653 , H04N21/4305 , H04N21/431 , H04N21/4316 , H04N21/434 , H04N21/43632 , H04N21/439 , H04N21/44 , H04N21/443 , H04N21/47
摘要： An on-screen display with variable resolution capability permits respective parts of a screen to be processed according to their respective resolution requirements. For any active window in the on-screen display, the data format used in memory to represent the pixels of that window can be determined, thereby permitting the window resolution to vary from window to window.
摘要翻译：具有可变分辨率能力的屏幕显示允许屏幕的相应部分根据其各自的分辨率要求进行处理。对于屏幕显示中的任何活动窗口，可以确定用于表示该窗口的像素的存储器中使用的数据格式，从而允许窗口分辨率随窗口而变化。

3. 发明授权

US5642437A System decoder circuit with temporary bit storage and method of operation 失效
标题翻译：具有临时位存储的系统解码电路和操作方法
公开(公告)号：US5642437A
公开(公告)日：1997-06-24
申请号：US54126
申请日：1993-04-26
申请人： Frank L. Laczko, Sr. , Gerard Benbassat , Stephen H. Li
发明人： Frank L. Laczko, Sr. , Gerard Benbassat , Stephen H. Li
IPC分类号： G06T9/00 , H04B1/66 , H04N5/04 , H04N5/60 , H04N7/26 , H04N7/50 , H04N21/2368 , H04N21/434 , H04S1/00 , H03M7/40
CPC分类号： H04S1/007 , H04B1/665 , H04N19/00 , H04N19/42 , H04N19/44 , H04N19/61 , H04N21/42607 , H04N21/4307 , H04N21/4341 , H04N21/4398 , H04N5/602 , H04N19/13 , H04N19/70 , H04N19/91 , H04N21/4305 , H04N5/04
摘要： A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).
摘要翻译：公开了一种数据处理系统（10），其包括耦合到解码系统（14）的微处理器主机（12）。主机接口块（18）接收比特流并将比特流传送到系统解码器块（20）。系统解码器块（20）从比特流中提取适当的数据，并加载输入缓冲器（24）或可选的外部缓冲器（26）。音频解码器块（28）从输入缓冲器（24）检索数据，并生成比例因子索引，存储在运算单元缓冲器（30）中的每码字值比特和子带样本。硬件滤波器运算单元块（32）从算术单元缓冲器（30）检索信息，对数据进行去量化，变换和滤波，以产生加载到PCM缓冲器（34）中的PCM输出数据。 PCM缓冲器（34）内的数据由PCM输出块（36）输出到数 - 模转换器（16）。

4. 发明授权

US5963596A Audio decoder circuit and method of operation 失效
标题翻译：音频解码电路及操作方法
公开(公告)号：US5963596A
公开(公告)日：1999-10-05
申请号：US857976
申请日：1997-05-16
申请人： Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Karen L. Walker , Shiu Wai Kam
发明人： Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Karen L. Walker , Shiu Wai Kam
IPC分类号： G06T9/00 , H04B1/66 , G06F11/00 , H04N7/68
CPC分类号： H04B1/665 , G06T9/004 , G06T9/007
摘要： A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).
摘要翻译：公开了一种数据处理系统（10），其包括耦合到解码系统（14）的微处理器主机（12）。主机接口块（18）接收比特流并将比特流传送到系统解码器块（20）。系统解码器块（20）从比特流中提取适当的数据，并加载输入缓冲器（24）或可选的外部缓冲器（26）。音频解码器块（28）从输入缓冲器（24）检索数据，并生成比例因子索引，存储在运算单元缓冲器（30）中的每码字值比特和子带样本。硬件滤波器运算单元块（32）从算术单元缓冲器（30）检索信息，对数据进行去量化，变换和滤波，以产生加载到PCM缓冲器（34）中的PCM输出数据。 PCM缓冲器（34）内的数据由PCM输出块（36）输出到数 - 模转换器（16）。

5. 发明授权

US5794181A Method for processing a subband encoded audio data stream 失效
标题翻译：用于处理子带编码音频数据流的方法
公开(公告)号：US5794181A
公开(公告)日：1998-08-11
申请号：US824072
申请日：1997-03-24
申请人： Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Kenneth R. Cyr , Jonathan L. Rowlands
发明人： Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Kenneth R. Cyr , Jonathan L. Rowlands
IPC分类号： G06T9/00 , H04B1/66 , G10L3/02 , G10L9/00
CPC分类号： H04B1/665 , G06T9/004 , G06T9/007
摘要： A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).
摘要翻译：公开了一种数据处理系统（10），其包括耦合到解码系统（14）的微处理器主机（12）。主机接口块（18）接收比特流并将比特流传送到系统解码器块（20）。系统解码器块（20）从比特流中提取适当的数据，并加载输入缓冲器（24）或可选的外部缓冲器（26）。音频解码器块（28）从输入缓冲器（24）检索数据，并生成比例因子索引，存储在运算单元缓冲器（30）中的每码字值比特和子带样本。硬件滤波器运算单元块（32）从算术单元缓冲器（30）检索信息，对数据进行去量化，变换和滤波，以产生加载到PCM缓冲器（34）中的PCM输出数据。 PCM缓冲器（34）内的数据由PCM输出块（36）输出到数 - 模转换器（16）。

6. 发明授权

US06369855B1 Audio and video decoder circuit and system 失效
标题翻译：音视频解码电路和系统
公开(公告)号：US06369855B1
公开(公告)日：2002-04-09
申请号：US08962514
申请日：1997-10-31
申请人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
发明人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
IPC分类号： H04N726
CPC分类号： H04N21/8166 , G09G5/14 , G09G5/395 , G09G2340/04 , G09G2340/125 , G09G2360/02 , H04L29/06 , H04L69/22 , H04N5/44 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N7/0882 , H04N11/20 , H04N19/42 , H04N19/61 , H04N21/42204 , H04N21/426 , H04N21/42615 , H04N21/42623 , H04N21/42653 , H04N21/4305 , H04N21/431 , H04N21/4316 , H04N21/434 , H04N21/43632 , H04N21/439 , H04N21/44 , H04N21/443 , H04N21/47
摘要： An improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC/PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessors circuit, an address bus connected to said circuits, and a data bus connected to said circuits.
摘要翻译：提供了一种改进的视听电路，其包括用于接收传输数据分组流的传输分组解析电路，用于初始化所述集成电路并用于处理所述数据分组流的部分的CPU电路，用于存储数据的ROM电路，RAM 用于存储数据的电路，用于解码所述数据分组流的音频部分的音频解码器电路，用于解码所述数据分组流的视频部分的视频解码器电路，用于对所述数据分组流的视频部分进行编码的NTSC / PAL编码电路， OSD协处理器电路，用于处理所述数据分组的OSD部分，业务控制器电路，在所述集成电路的部分之间移动所述数据分组流的部分，扩展总线接口电路，P1394接口电路，通信协处理器电路，连接的地址总线连接到所述电路，以及连接到所述电路的数据总线。

7. 发明授权

US5729556A System decoder circuit with temporary bit storage and method of operation 失效
标题翻译：具有临时位存储的系统解码电路和操作方法
公开(公告)号：US5729556A
公开(公告)日：1998-03-17
申请号：US54127
申请日：1993-04-26
申请人： Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Karen L. Walker , Shiu Wai Kam
发明人： Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Karen L. Walker , Shiu Wai Kam
IPC分类号： G06T9/00 , H04B1/66 , G06F11/00 , H04N7/68
CPC分类号： H04B1/665 , G06T9/004 , G06T9/007
摘要： A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).
摘要翻译：公开了一种数据处理系统（10），其包括耦合到解码系统（14）的微处理器主机（12）。主机接口块（18）接收比特流并将比特流传送到系统解码器块（20）。系统解码器块（20）从比特流中提取适当的数据，并加载输入缓冲器（24）或可选的外部缓冲器（26）。音频解码器块（28）从输入缓冲器（24）检索数据，并生成比例因子索引，存储在运算单元缓冲器（30）中的每码字值比特和子带样本。硬件滤波器运算单元块（32）从算术单元缓冲器（30）检索信息，对数据进行去量化，变换和滤波，以产生加载到PCM缓冲器（34）中的PCM输出数据。 PCM缓冲器（34）内的数据由PCM输出块（36）输出到数 - 模转换器（16）。

8. 发明授权

US5657454A Audio decoder circuit and method of operation 失效
标题翻译：音频解码电路及操作方法
公开(公告)号：US5657454A
公开(公告)日：1997-08-12
申请号：US477028
申请日：1995-06-07
申请人： Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Karen L. Walker , Shiu Wai Kam
发明人： Gerard Benbassat , Frank L. Laczko, Sr. , Stephen H. Li , Karen L. Walker , Shiu Wai Kam
IPC分类号： G06T9/00 , H04B1/66 , H04N5/04 , H04N5/60 , H04N7/26 , H04N7/50 , H04N21/2368 , H04N21/434 , H04S1/00 , G06F17/00
CPC分类号： H04S1/007 , H04B1/665 , H04N19/00 , H04N19/42 , H04N19/44 , H04N19/61 , H04N21/42607 , H04N21/4307 , H04N21/4341 , H04N21/4398 , H04N5/602 , H04N19/13 , H04N19/70 , H04N19/91 , H04N21/4305 , H04N5/04
摘要： A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).
摘要翻译：公开了一种数据处理系统（10），其包括耦合到解码系统（14）的微处理器主机（12）。主机接口块（18）接收比特流并将比特流传送到系统解码器块（20）。系统解码器块（20）从比特流中提取适当的数据，并加载输入缓冲器（24）或可选的外部缓冲器（26）。音频解码器块（28）从输入缓冲器（24）检索数据，并生成比例因子索引，存储在运算单元缓冲器（30）中的每码字值比特和子带样本。硬件滤波器运算单元块（32）从算术单元缓冲器（30）检索信息，对数据进行去量化，变换和滤波，以产生加载到PCM缓冲器（34）中的PCM输出数据。 PCM缓冲器（34）内的数据由PCM输出块（36）输出到数 - 模转换器（16）。

9. 发明授权

US5631848A System decoder circuit and method of operation 失效
标题翻译：系统解码电路及操作方法
公开(公告)号：US5631848A
公开(公告)日：1997-05-20
申请号：US486487
申请日：1995-06-07
申请人： Frank L. Laczko, Sr. , Gerard Benbassat , Stephen H. Li
发明人： Frank L. Laczko, Sr. , Gerard Benbassat , Stephen H. Li
IPC分类号： G06T9/00 , H04B1/66 , H04N5/04 , H04N5/60 , H04N7/26 , H04N7/50 , H04N21/2368 , H04N21/434 , H04S1/00 , G06F19/00
CPC分类号： H04S1/007 , H04B1/665 , H04N19/00 , H04N19/42 , H04N19/44 , H04N19/61 , H04N21/42607 , H04N21/4307 , H04N21/4341 , H04N21/4398 , H04N5/602 , H04N19/13 , H04N19/70 , H04N19/91 , H04N21/4305 , H04N5/04
摘要： A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).
摘要翻译：公开了一种数据处理系统（10），其包括耦合到解码系统（14）的微处理器主机（12）。主机接口块（18）接收比特流并将比特流传送到系统解码器块（20）。系统解码器块（20）从比特流中提取适当的数据，并加载输入缓冲器（24）或可选的外部缓冲器（26）。音频解码器块（28）从输入缓冲器（24）检索数据，并生成比例因子索引，存储在运算单元缓冲器（30）中的每码字值比特和子带样本。硬件滤波器运算单元块（32）从算术单元缓冲器（30）检索信息，对数据进行去量化，变换和滤波，以产生加载到PCM缓冲器（34）中的PCM输出数据。 PCM缓冲器（34）内的数据由PCM输出块（36）输出到数 - 模转换器（16）。

10. 发明授权

US06310657B1 Real time window address calculation for on-screen display 有权
标题翻译：屏幕显示实时窗口地址计算
公开(公告)号：US06310657B1
公开(公告)日：2001-10-30
申请号：US09679000
申请日：2000-10-04
申请人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
发明人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
IPC分类号： H04N550
CPC分类号： H04N21/8166 , G09G5/14 , G09G5/395 , G09G2340/04 , G09G2340/125 , G09G2360/02 , H04L29/06 , H04L69/22 , H04N5/44 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N7/0882 , H04N11/20 , H04N19/42 , H04N19/61 , H04N21/42204 , H04N21/426 , H04N21/42615 , H04N21/42623 , H04N21/42653 , H04N21/4305 , H04N21/431 , H04N21/4316 , H04N21/434 , H04N21/43632 , H04N21/439 , H04N21/44 , H04N21/443 , H04N21/47
摘要： An on-screen display system in which a CPU generates windows in a working memory space also provides for real time calculation of window addresses in the working memory space. This can eliminate the need for a separate frame buffer memory.
摘要翻译：其中CPU在工作存储器空间中生成窗口的屏幕显示系统还提供对工作存储器空间中的窗口地址的实时计算。这可以消除对单独的帧缓冲存储器的需要。

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