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11. 发明授权

US09455691B2 Flip-flop cell with configurable delay 有权
标题翻译：具有可配置延迟的触发器单元
公开(公告)号：US09455691B2
公开(公告)日：2016-09-27
申请号：US14516680
申请日：2014-10-17
申请人： Gaurav Goyal , Ashis Maitra , Ateet Mishra
发明人： Gaurav Goyal , Ashis Maitra , Ateet Mishra
IPC分类号： H03K3/3562 , H03K19/173
CPC分类号： H03K3/35625 , H03K19/1737
摘要： Flip-flop cells that enable time borrowing during the design of the IC to improve setup times while avoiding introducing meta-stability, and alternatively to avoid hold time violations. The flip-flop cells are connected with logic cells in functional data paths. The flip-flop cell has a clock signal controlling both its input and output. A selective delay cell selectively delays either a data signal input to the flip-flop cell or the clock signal controlling the flip-flop cell. The selectively delayed signal adjusts the timing (setup, hold and clock-to-output) of the data path.
摘要翻译：触发器单元，在IC的设计期间能够借用时间来改善建立时间，同时避免引入元稳定性，并且可选地避免持续时间违规。触发器单元与功能数据路径中的逻辑单元相连。触发器单元具有控制其输入和输出的时钟信号。选择性延迟单元选择性地延迟输入到触发器单元的数据信号或控制触发器单元的时钟信号。选择性延迟的信号调整数据路径的定时（建立，保持和时钟到输出）。

12. 发明授权

US09438248B2 Low power digital self-gated binary counter 有权
标题翻译：低功率数字自门控二进制计数器
公开(公告)号：US09438248B2
公开(公告)日：2016-09-06
申请号：US14568115
申请日：2014-12-12
申请人： Naman Gupta , Amol Agarwal , Gaurav Goyal
发明人： Naman Gupta , Amol Agarwal , Gaurav Goyal
IPC分类号： H03K21/00 , H03K23/40 , H03K21/12 , H03K21/38 , H03K23/58 , H03K23/00
CPC分类号： H03K23/40 , H03K21/00 , H03K21/12 , H03K21/38 , H03K23/00 , H03K23/58
摘要： An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The control logic includes a clock-gating integrated cell arranged to clock gate at least one higher-order counter sub-module dependent on a logical combination of outputs of the lower-order counter sub-module and to provide a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules. The control logic does not include any intervening memory device between the lower-order counter sub-module and the clock-gating integrated cell for use in determining a later control logic output.
摘要翻译： n位计数器由级联计数器子模块形成。计数器包括耦合到低阶计数器子模块的组合控制逻辑。控制逻辑包括时钟门控集成单元，其布置成根据低阶计数器子模块的输出的逻辑组合对至少一个高阶计数器子模块进行时钟门控，并提供用于分辨率的多循环路径任何后续级联计数器子模块的输出的逻辑组合。控制逻辑不包括在低阶计数器子模块和时钟门控集成单元之间的任何中间存储器件，用于确定稍后的控制逻辑输出。

13. 发明申请

US20160173106A1 LOW POWER DIGITAL SELF-GATED BINARY COUNTER 有权
标题翻译：低功率数字自选二进制计数器
公开(公告)号：US20160173106A1
公开(公告)日：2016-06-16
申请号：US14568115
申请日：2014-12-12
申请人： Naman Gupta , Amol Agarwal , Gaurav Goyal
发明人： Naman Gupta , Amol Agarwal , Gaurav Goyal
IPC分类号： H03K23/40 , H03K21/00
CPC分类号： H03K23/40 , H03K21/00 , H03K21/12 , H03K21/38 , H03K23/00 , H03K23/58
摘要： An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The control logic includes a clock-gating integrated cell arranged to clock gate at least one higher-order counter sub-module dependent on a logical combination of outputs of the lower-order counter sub-module and to provide a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules. The control logic does not include any intervening memory device between the lower-order counter sub-module and the clock-gating integrated cell for use in determining a later control logic output.
摘要翻译： n位计数器由级联计数器子模块形成。计数器包括耦合到低阶计数器子模块的组合控制逻辑。控制逻辑包括时钟门控集成单元，其布置成根据低阶计数器子模块的输出的逻辑组合对至少一个高阶计数器子模块进行时钟门控，并提供用于分辨率的多循环路径任何后续级联计数器子模块的输出的逻辑组合。控制逻辑不包括在低阶计数器子模块和时钟门控集成单元之间的任何中间存储器件，用于确定稍后的控制逻辑输出。

14. 发明授权

US09331516B2 Single power supply level shifter 有权
标题翻译：单电源电平转换器
公开(公告)号：US09331516B2
公开(公告)日：2016-05-03
申请号：US14280655
申请日：2014-05-18
申请人： Gaurav Goyal
发明人： Gaurav Goyal
IPC分类号： H03L5/00 , H02J7/02 , H02J7/00 , H02J7/04 , H03K19/0185 , H02J7/34
CPC分类号： H02J7/022 , H02J7/0042 , H02J7/045 , H02J7/345 , H02J2001/008 , H03K19/01707 , H03K19/018521
摘要： A single power supply level shifter has first and second inverters in tandem that invert an input signal from a first voltage domain and provide a first inverted signal and an output signal in a second voltage domain. A charging control circuit charges a capacitor towards the second voltage when the input signal is high, and conducts a discharge current from the capacitor during a transition of the input signal from high to low to accelerate a corresponding transition of the first inverted signal from low to high. A third inverter controls a current reduction transistor in series with the first inverter, and a third control transistor connected between the input and the charging control circuit to accelerate the flow of discharge current during the transition of the input signal from high to low.
摘要翻译：单个电源电平移位器具有串联的第一和第二反相器，它们反转来自第一电压域的输入信号，并在第二电压域中提供第一反相信号和输出信号。当输入信号为高电平时，充电控制电路使电容器朝向第二电压充电，并且在输入信号从高电平变化到低电平期间，从电容器传导放电电流，以加速第一反相信号从低电平到第高。第三反相器控制与第一反相器串联的电流减小晶体管，以及连接在输入和充电控制电路之间的第三控制晶体管，以在输入信号从高变为低期间加速放电电流的流动。

15. 发明申请

US20160112036A1 FLIP-FLOP CELL WITH CONFIGURABLE DELAY 有权
标题翻译：具有可配置延迟的FLIP-FLOP单元
公开(公告)号：US20160112036A1
公开(公告)日：2016-04-21
申请号：US14516680
申请日：2014-10-17
申请人： Gaurav Goyal , Ashis Maitra , Ateet Mishra
发明人： Gaurav Goyal , Ashis Maitra , Ateet Mishra
IPC分类号： H03K3/3562
CPC分类号： H03K3/35625 , H03K19/1737
摘要： Flip-flop cells that enable time borrowing during the design of the IC to improve setup times while avoiding introducing meta-stability, and alternatively to avoid hold time violations. The flip-flop cells are connected with logic cells in functional data paths. The flip-flop cell has a clock signal controlling both its input and output. A selective delay cell selectively delays either a data signal input to the flip-flop cell or the clock signal controlling the flip-flop cell. The selectively delayed signal adjusts the timing (setup, hold and clock-to-output) of the data path.
摘要翻译：触发器单元，在IC的设计期间能够借用时间来改善建立时间，同时避免引入元稳定性，并且可选地避免持续时间违规。触发器单元与功能数据路径中的逻辑单元相连。触发器单元具有控制其输入和输出的时钟信号。选择性延迟单元选择性地延迟输入到触发器单元的数据信号或控制触发器单元的时钟信号。选择性延迟的信号调整数据路径的定时（建立，保持和时钟到输出）。

16. 发明授权

US09312834B1 Low leakage flip-flop circuit 有权
标题翻译：低漏电触发器电路
公开(公告)号：US09312834B1
公开(公告)日：2016-04-12
申请号：US14591924
申请日：2015-01-08
申请人： Mohit Parnami , Gaurav Goyal
发明人： Mohit Parnami , Gaurav Goyal
IPC分类号： H03K3/356 , H03K3/3562
CPC分类号： H03K3/35625 , H03K3/012
摘要： An integrated circuit having reduced power consumption includes a clock-gating cell, a transistor and a flip-flop. The clock-gating cell receives a dynamic enable signal, generates a latched-enable signal and gates a clock signal provided to the flip-flop. The flip-flop includes first and second latches. The transistor receives an inverted latched-enable signal from the clock-gating cell and switches ON or OFF based on the logic state of the inverted latched-enable signal. The transistor provides a voltage signal to the flip-flop circuit based on the state of the flip-flop in order to control the state of the flip-flop, which reduces power consumption of the integrated circuit.
摘要翻译：具有降低功耗的集成电路包括时钟门控单元，晶体管和触发器。时钟门控单元接收动态使能信号，产生锁存使能信号并门控提供给触发器的时钟信号。触发器包括第一和第二锁存器。晶体管从时钟门控单元接收反向锁存使能信号，并根据反相锁存使能信号的逻辑状态接通或断开。晶体管基于触发器的状态向触发器电路提供电压信号，以便控制触发器的状态，这降低了集成电路的功耗。

17. 发明授权

US09081061B1 Scan flip-flop 有权
标题翻译：扫描触发器
公开(公告)号：US09081061B1
公开(公告)日：2015-07-14
申请号：US14262789
申请日：2014-04-27
申请人： Amol Agarwal , Gaurav Goyal , Reecha Jajodia
发明人： Amol Agarwal , Gaurav Goyal , Reecha Jajodia
IPC分类号： H03K19/173 , G01R31/3177
CPC分类号： G01R31/318541
摘要： A scan flip-flop includes a multiplexer, a flip-flop, and a logic circuit. The flip-flop includes a transmission gate that has two sets of clock-controlled transistors. The combined width of the clock-controlled transistors in a set equals the width of the single transistor commonly used in known scan flip-flop circuits. The logic circuit inhibits the clock signal from reaching one transistor of each set during scan mode, which reduces power consumption without sacrificing speed of operation.
摘要翻译：扫描触发器包括多路复用器，触发器和逻辑电路。触发器包括具有两组时钟控制晶体管的传输门。集合中的时钟控制晶体管的组合宽度等于已知扫描触发器电路中常用的单个晶体管的宽度。逻辑电路在扫描模式期间阻止时钟信号到达每组的一个晶体管，这降低了功耗，而不牺牲操作速度。

18. 发明申请

US20150010124A1 DIGITAL SELF-GATED BINARY COUNTER 有权
标题翻译：数字自选二进制计数器
公开(公告)号：US20150010124A1
公开(公告)日：2015-01-08
申请号：US13935552
申请日：2013-07-04
申请人： Naman Gupta , Amol Agarwal , Gaurav Goyal
发明人： Naman Gupta , Amol Agarwal , Gaurav Goyal
IPC分类号： H03K23/40
CPC分类号： H03K23/40 , H03K21/00 , H03K21/12 , H03K21/38 , H03K23/00 , H03K23/58
摘要： An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output.
摘要翻译： n位计数器由级联计数器子模块形成。计数器包括耦合到低阶计数器子模块的组合控制逻辑。控制逻辑被配置为根据低阶计数器子模块的输出的逻辑组合对至少一个更高阶计数器子模块进行时钟门控，并且其中控制逻辑使用流水线存储至少一个先前控制逻辑输出以供使用在确定稍后的控制逻辑输出时。

19. 发明授权

US09311438B1 Signal delay flip-flop cell for fixing hold time violation 有权
标题翻译：用于固定保持时间违规的信号延迟触发器单元
公开(公告)号：US09311438B1
公开(公告)日：2016-04-12
申请号：US14509037
申请日：2014-10-07
申请人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidhartha Taneja
发明人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidhartha Taneja
IPC分类号： G06F17/50 , H03K3/037 , H03K3/012
CPC分类号： G06F17/5031 , G06F2217/02 , G06F2217/84 , H03K3/012 , H03K3/0372 , H03K3/0375
摘要： A signal delay cell for use in resolving hold time violations in an IC has a first multiplexer having a first functional data input node and a scan data input node TI and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. The signal delay cell is available to replace a flip-flop having a scan data hold problem, and also for use in solving a functional data violation in the same or another cell.
摘要翻译：用于解决IC中的保持时间冲突的信号延迟单元具有第一多路复用器，其具有第一功能数据输入节点和扫描数据输入节点TI，第二多路复用器具有第二功能数据输入节点，第二输入节点连接到第一多路复用器和触发器模块的输出。施加到第一多路复用器的数据输入信号的传播被延迟，并且通过第一多路复用器的传输来增加触发器模块的保持余量。信号延迟单元可用于替换具有扫描数据保持问题的触发器，并且还用于解决相同或另一个单元中的功能数据违例。

20. 发明申请

US20160098506A1 SIGNAL DELAY FLIP-FLOP CELL FOR FIXING HOLD TIME VIOLATION 有权
标题翻译：信号延迟翻转细胞固定持续时间
公开(公告)号：US20160098506A1
公开(公告)日：2016-04-07
申请号：US14509037
申请日：2014-10-07
申请人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidharrtha Taneja
发明人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidharrtha Taneja
IPC分类号： G06F17/50 , H03K3/012 , H03K3/037
CPC分类号： G06F17/5031 , G06F2217/02 , G06F2217/84 , H03K3/012 , H03K3/0372 , H03K3/0375
摘要： A signal delay cell for use in resolving hold time violations in an IC has a first multiplexer having a first functional data input node and a scan data input node TI and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. The signal delay cell is available to replace a flip-flop having a scan data hold problem, and also for use in solving a functional data violation in the same or another cell.
摘要翻译：用于解决IC中的保持时间冲突的信号延迟单元具有第一多路复用器，其具有第一功能数据输入节点和扫描数据输入节点TI，第二多路复用器具有第二功能数据输入节点，第二输入节点连接到第一多路复用器和触发器模块的输出。施加到第一多路复用器的数据输入信号的传播被延迟，并且通过第一多路复用器的传输来增加触发器模块的保持余量。信号延迟单元可用于替换具有扫描数据保持问题的触发器，并且还用于解决相同或另一个单元中的功能数据违例。

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