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11. 发明授权

US06728838B2 Cache operation based on range of addresses 有权
标题翻译：基于地址范围的缓存操作
公开(公告)号：US06728838B2
公开(公告)日：2004-04-27
申请号：US09932634
申请日：2001-08-17
申请人： Gerard Chauvel , Serge Lasserre
发明人： Gerard Chauvel , Serge Lasserre
IPC分类号： G06F1212
CPC分类号： G06F1/329 , G06F1/206 , G06F1/3203 , G06F9/30047 , G06F12/0292 , G06F12/0804 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (1806(n). Validity circuitry (VI) and dirty bit circuitry (DI) is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Block circuitry (700, 702) is connected to the set of valid bits and dirty bits and is operable to invalidate a selected range of lines in response to a directive from the first processor. The block circuitry has a start register (700) and an end register (702) each separately loadable by the processor. The block circuitry can invalidate either a single line or a block of lines in response to an operation command from the processor, depending on whether the end register is loaded or not. Likewise, the block circuitry can clean a single line or a block of lines in response to an operation command from the processor.
摘要翻译：提供了一种数字系统和操作方法，其中数字系统具有至少一个处理器，具有相关联的多段高速缓冲存储器电路（1806（n）），有效电路（VI）和脏位电路（DI）连接到存储器电路并且可操作以指示多个段中的每个段是否保存有效数据。块电路（700,702）连接到该组有效位和脏位，并且可操作以使响应中的所选行范围无效块电路具有开始寄存器（700）和结束寄存器（702），每个开关寄存器（700）和终端寄存器（702）都可以由处理器分别加载。块电路可以响应于第一处理器使单行或一组线路无效来自处理器的操作命令，取决于结束寄存器是否被加载。同样地，块电路可以响应于来自处理器的操作命令来清除单行或一行线。

12. 发明授权

US06310657B1 Real time window address calculation for on-screen display 有权
标题翻译：屏幕显示实时窗口地址计算
公开(公告)号：US06310657B1
公开(公告)日：2001-10-30
申请号：US09679000
申请日：2000-10-04
申请人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
发明人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
IPC分类号： H04N550
CPC分类号： H04N21/8166 , G09G5/14 , G09G5/395 , G09G2340/04 , G09G2340/125 , G09G2360/02 , H04L29/06 , H04L69/22 , H04N5/44 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N7/0882 , H04N11/20 , H04N19/42 , H04N19/61 , H04N21/42204 , H04N21/426 , H04N21/42615 , H04N21/42623 , H04N21/42653 , H04N21/4305 , H04N21/431 , H04N21/4316 , H04N21/434 , H04N21/43632 , H04N21/439 , H04N21/44 , H04N21/443 , H04N21/47
摘要： An on-screen display system in which a CPU generates windows in a working memory space also provides for real time calculation of window addresses in the working memory space. This can eliminate the need for a separate frame buffer memory.
摘要翻译：其中CPU在工作存储器空间中生成窗口的屏幕显示系统还提供对工作存储器空间中的窗口地址的实时计算。这可以消除对单独的帧缓冲存储器的需要。

13. 发明授权

US07757067B2 Pre-decoding bytecode prefixes selectively incrementing stack machine program counter 有权
标题翻译：预解码字节码前缀选择性地递增堆栈机器程序计数器
公开(公告)号：US07757067B2
公开(公告)日：2010-07-13
申请号：US10632222
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Maija Kuusela
发明人： Gerard Chauvel , Serge Lasserre , Maija Kuusela
IPC分类号： G06F9/30 , G06F9/40
CPC分类号： G06F9/30149 , G06F9/30076 , G06F9/30181 , G06F9/30185 , G06F9/382 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A processor (e.g., a co-processor) comprising a decoder coupled to a pre-decoder, in which the decoder decodes a current instruction in parallel with the pre-decoder pre-decoding a subsequent instruction. In particular, the pre-decoder examines at least five Bytecodes in parallel with the decoder decoding a current instruction. The pre-decoder determines if a subsequent instruction contains a prefix. If a prefix is detected in at least one of the five Bytecodes, a program counter skips the prefix and changes the behavior of the decoder during the decoding of the subsequent instruction.
摘要翻译：包括耦合到预解码器的解码器的处理器（例如，协处理器），其中解码器与预解码器并行地解码当前指令，以对后续指令进行解码。特别地，预解码器与解码器解码当前指令并行地检查至少五个字节码。预解码器确定后续指令是否包含前缀。如果在五个字节码中的至少一个中检测到前缀，则程序计数器跳过前缀，并且在后续指令的解码期间改变解码器的行为。

14. 发明授权

US07496930B2 Accessing device driver memory in programming language representation 有权
标题翻译：以编程语言表示访问设备驱动程序内存
公开(公告)号：US07496930B2
公开(公告)日：2009-02-24
申请号：US10831575
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F13/00
CPC分类号： G09G5/39 , G06F3/14 , G09G5/393
摘要： In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application software comprises instructions that initialize an application data structure (e.g., an object or array) usable by the application software to manage the device and also comprises instructions that map the application data structure to a memory associated with the device without the use of a device driver. In other embodiments, a method comprises initializing an application data structure to manage a hardware device and mapping the application data structure to a memory associated with the hardware device without the use of a device driver. The application data structure may store a single dimensional data structure or a multi-dimensional data structure. In some embodiments, the device being managed by the application software may comprise a display and the application software may comprise Java code.
摘要翻译：在一些实施例中，存储介质包括执行一个或多个操作并直接管理设备的应用软件。应用软件包括初始化应用软件可用于管理设备的应用数据结构（例如，对象或阵列）的指令，还包括将应用数据结构映射到与设备相关联的存储器而不使用设备驱动。在其他实施例中，一种方法包括初始化应用数据结构以管理硬件设备，并将应用数据结构映射到与硬件设备相关联的存储器，而不使用设备驱动程序。应用数据结构可以存储单维数据结构或多维数据结构。在一些实施例中，由应用软件管理的设备可以包括显示器，并且应用软件可以包括Java代码。

15. 发明申请

US20050033945A1 Dynamically changing the semantic of an instruction 审中-公开
标题翻译：动态地改变指令的语义
公开(公告)号：US20050033945A1
公开(公告)日：2005-02-10
申请号：US10830917
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banatre , Jean-Paul Routeau , Salam Majoul , Frederic Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banatre , Jean-Paul Routeau , Salam Majoul , Frederic Parain
IPC分类号： G06F9/22 , G06F9/318 , G06F9/44 , G06F11/34 , G06F12/00 , G06F9/30
CPC分类号： G06F11/3466 , G06F9/30087 , G06F9/30174 , G06F9/30189 , G06F2201/865 , G06F2201/88
摘要： A technique comprises receiving an instruction and dynamically changing the instruction's semantic based on programmable information that is separate from the instruction. The change in semantic may comprise the inclusion of monitoring code that determines a performance characteristic associated with the instruction or a change in the instruction's operation (e.g., the inclusion of read or write barrier operations to support a garbage collector).
摘要翻译：一种技术包括接收指令并基于与指令分离的可编程信息来动态地改变指令的语义。语义的变化可以包括包括确定与指令相关联的性能特征的监视代码或指令的操作的改变（例如，包括用于支持垃圾收集器的读取或写入屏障操作）。

16. 发明授权

US06826652B1 Smart cache 有权
标题翻译：智能缓存
公开(公告)号：US06826652B1
公开(公告)日：2004-11-30
申请号：US09591537
申请日：2000-06-09
申请人： Gerard Chauvel , Serge Lasserre , Dominique Benoit Jacques D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Dominique Benoit Jacques D'Inverno
IPC分类号： G06F1208
CPC分类号： G06F12/0897 , G06F2212/2515
摘要： A cache architecture (16) for use in a processing includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20). The hit/miss logic (46) also determines whether a line should be loaded into the RAM set data array (38) or in the associated cache.
摘要翻译：用于处理的缓存结构（16）包括用于缓存主存储器（20）的连续块的RAM集缓存。 RAM集缓存可以与其他缓存类型一起使用，例如集合关联高速缓存或直接映射高速缓存。寄存器（32）定义主存储器（20）的连续块的起始地址。与RAM组相关联的数据阵列（38）可以逐行填充，因为处理核心请求线路，或者在开始时填充数据阵列（38）的设置填充基础上地址被加载到寄存器（32）中。由于从处理核心接收到地址，因此使用命中/未命中逻辑（46）起始地址寄存器（32），全局有效位（34），行有效位（37）和控制位（24,26）来确定数据是否存在于RAM集合中，或者数据是否必须从主存储器（20）加载。命中/未命中逻辑（46）还确定是否将线路加载到RAM集数据阵列（38）或相关联的高速缓存中。

17. 发明授权

US06751706B2 Multiple microprocessors with a shared cache 有权
标题翻译：具有共享缓存的多个微处理器
公开(公告)号：US06751706B2
公开(公告)日：2004-06-15
申请号：US09932651
申请日：2001-08-17
申请人： Gerard Chauvel , Maija Kuusela , Dominique D'Inverno , Serge Lasserre
发明人： Gerard Chauvel , Maija Kuusela , Dominique D'Inverno , Serge Lasserre
IPC分类号： G06F1200
CPC分类号： G06F9/5011 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30043 , G06F9/5094 , G06F11/3409 , G06F12/0292 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/815 , G06F2201/86 , G06F2201/88 , G06F2201/885 , G06F2209/5014 , G06F2209/5021 , G06F2209/507 , G06F2212/1028 , G06F2212/681 , Y02D10/13 , Y02D10/16 , Y02D10/22 , Y02D10/24 , Y02D10/34
摘要： A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. When the L2-cache misses, the penalty to access to data within the L3 memory is high. The system supports miss under miss to let a second miss interrupt a segment prefetch being done in response to a first miss. Thus, an interruptible SDRAM to L2-cache prefetch system with miss under miss support is provided. A shared translation look-aside buffer (TLB) is provided for L2 accesses, while a private TLB is associated with each processor. A micro TLB (&mgr;TLB) is associated with each resource that can initiate a memory transfer. The L2 cache, along with all of the TLBs and &mgr;TLBs have resource ID fields and task ID fields associated with each entry to allow flushing and cleaning based on resource or task. Configuration circuitry is provided to allow the digital system to be configured on a task by task basis in order to reduce power consumption.
摘要翻译：数字系统具有几个处理器，与每个处理器相关联的私有一级（L1）高速缓存，每个条目具有多个段的共享二级（L2）高速缓存以及三级（L3）物理存储器。共享的L2高速缓存体系结构体现为4路关联性，每个条目有4个段和4个有效位和脏位。当L2缓存未命中时，访问L3内存中的数据的惩罚很高。该系统支持未命中错过，以使第二个错误中断一个段预取正在响应于第一个错过。因此，提供了一个可中断的SDRAM到L2缓存预取系统，其中错过了支持。为L2访问提供共享翻译后备缓冲器（TLB），而私有TLB与每个处理器相关联。微型TLB（muTLB）与可以启动存储器传输的每个资源相关联。 L2缓存以及所有TLB和muTLB都具有与每个条目关联的资源ID字段和任务ID字段，以允许基于资源或任务的冲洗和清理。提供配置电路以允许数字系统根据任务在任务上进行配置，以便降低功耗。

18. 发明授权

US06745293B2 Level 2 smartcache architecture supporting simultaneous multiprocessor accesses 有权
标题翻译： 2级smartcache架构支持同时多处理器访问
公开(公告)号：US06745293B2
公开(公告)日：2004-06-01
申请号：US09932308
申请日：2001-08-17
申请人： Serge Lasserre , Gerard Chauvel
发明人： Serge Lasserre , Gerard Chauvel
IPC分类号： G06F1200
CPC分类号： G06F9/5011 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30043 , G06F12/084 , G06F12/0846 , G06F12/0879 , G06F12/0891 , G06F2201/81 , G06F2201/885 , G06F2209/5021 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. Multiple detection circuitry responds to several cache access requests concurrently. Multiple ports in the cache service multiple requesters concurrently if concurrent hits are determined by the detection circuitry.
摘要翻译：数字系统具有几个处理器，与每个处理器相关联的私有一级（L1）高速缓存，每个条目具有多个段的共享二级（L2）高速缓存以及三级（L3）物理存储器。共享的L2高速缓存体系结构体现为4路关联性，每个条目有4个段和4个有效位和脏位。多个检测电路同时响应多个缓存访问请求。如果并发命中由检测电路确定，高速缓存服务中的多个端口将同时发送多个请求者。

19. 发明授权

US08539159B2 Dirty cache line write back policy based on stack size trend information 有权
标题翻译：基于堆栈大小趋势信息的脏缓存行回写策略
公开(公告)号：US08539159B2
公开(公告)日：2013-09-17
申请号：US10631185
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F2212/502
摘要： Methods and apparatuses are disclosed for managing memory write back. In some embodiments, the method may include examining current and future instructions operating on a stack that exists in memory, determining stack trend information from the instructions, and utilizing the trend information to reduce data traffic between various levels of the memory. As stacked data are written to a cache line in a first level of memory, if future instructions indicate that additional cache lines are required for subsequent write operations within the stack, then the cache line may be written back to a second level of memory. If however, the future instructions indicate that no additional cache lines are required for subsequent write operations within the stack, then the first level of memory may avoid writing back the cache line and also may keep it marked as dirty.
摘要翻译：公开了用于管理存储器回写的方法和装置。在一些实施例中，该方法可以包括检查在存储器中存在的堆栈上操作的当前和未来指令，从指令确定堆栈趋势信息，以及利用趋势信息来减少存储器的各个级别之间的数据流量。当堆叠数据被写入第一级存储器中的高速缓存行时，如果未来的指令指示需要额外的高速缓存行用于堆栈内的后续写入操作，则高速缓存行可以被写回到第二级存储器。然而，如果未来的指令指示不需要额外的高速缓存行用于堆栈内的后续写入操作，则第一级存储器可以避免写回高速缓存行并且还可以将其标记为脏。

20. 发明授权

US08032891B2 Energy-aware scheduling of application execution 有权
标题翻译：能源感知调度应用程序执行
公开(公告)号：US08032891B2
公开(公告)日：2011-10-04
申请号：US10151282
申请日：2002-05-20
申请人： Gerard Chauvel , Dominique D'Inverno , Serge Lasserre , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Frédéric Parain , Jean-Paul Routeau , Salam Majoul
发明人： Gerard Chauvel , Dominique D'Inverno , Serge Lasserre , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Frédéric Parain , Jean-Paul Routeau , Salam Majoul
IPC分类号： G06F9/46 , G06F1/32
CPC分类号： G06F9/4881 , G06F1/3228 , G06F1/329 , Y02D10/24
摘要： A mobile device (10) manages tasks (18) using a scheduler (20) for scheduling tasks on multiple processors (12). To conserve energy, the set of tasks to be scheduled are divided into two (or more) subsets, which are scheduled according to different procedures. In a specific embodiment, the first subset contains tasks with the highest energy consumption deviation based on the processor that executes the task. This subset is scheduled according to a power-aware procedure for scheduling tasks primarily based on energy consumption criteria. If there is no failure, the second subset is scheduled according to a real-time constrained procedure that schedules tasks primarily based on the deadlines associated with the various tasks in the second subset. If there is a failure in either procedure, one or more tasks with the lowest energy consumption deviation are moved from the first subset to the second subset and the scheduling is repeated.
摘要翻译：移动设备（10）使用调度器（20）管理任务（18），用于在多个处理器（12）上调度任务。为了节约能源，要调度的任务集合分为两个（或多个）子集，根据不同的过程进行调度。在具体实施例中，第一子集基于执行任务的处理器包含具有最高能量消耗偏差的任务。该子集根据用于主要基于能量消耗标准的调度任务的功率感知程序进行调度。如果没有失败，则根据实时约束程序调度第二子集，该实时约束过程主要基于与第二子集中的各种任务相关联的期限来调度任务。如果任何一个过程都有故障，则能量消耗偏差最小的一个或多个任务从第一个子集移动到第二个子集，重复调度。

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