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11. 发明授权

US09330735B2 Memory with deferred fractional row activation 有权
$Memory with deferred fractional row activation$
标题翻译：具有延迟分数行激活的内存
公开(公告)号：US09330735B2
公开(公告)日：2016-05-03
申请号：US13640084
申请日：2012-06-08
申请人： James Edward Harris , Thomas Vogelsang , Frederick A. Ware , Ian P. Shaeffer
发明人： James Edward Harris , Thomas Vogelsang , Frederick A. Ware , Ian P. Shaeffer
IPC分类号： G11C7/00 , G11C7/06 , G11C5/02 , G11C7/10 , G11C11/4076 , G11C11/408 , G11C11/4091 , G11C7/08
CPC分类号： G11C7/1039 , G11C5/025 , G11C7/06 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/222 , G11C8/08 , G11C8/10 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the sub-row to be activated.
摘要翻译：存储器组件内的行激活操作相对于子行执行，而不是完整的存储行，以减少功耗。此外，除了响应于行命令激活子代以外，子代激活操作被延迟，直到接收到指定要执行的列操作的列命令和要被激活的子行。

12. 发明授权

US09287239B2 Techniques for interconnecting stacked dies using connection sites 有权
标题翻译：使用连接点互连堆叠管芯的技术
公开(公告)号：US09287239B2
公开(公告)日：2016-03-15
申请号：US13641680
申请日：2011-04-13
申请人： Frederick A. Ware , Ely Tsern , Thomas Vogelsang
发明人： Frederick A. Ware , Ely Tsern , Thomas Vogelsang
IPC分类号： H01L25/16 , H01L23/538 , H01L25/065 , H01L25/18 , H01L23/48
CPC分类号： H01L23/481 , G06F3/0604 , G06F3/0629 , G06F3/0673 , G06F2213/0038 , H01L25/0657 , H01L25/18 , H01L2224/131 , H01L2224/16146 , H01L2225/06544 , H01L2924/014
摘要： An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.
摘要翻译：集成电路管芯包括至少位于其连续区域内的集成电路管芯的表面上的导电连接位置。集成电路还包括位于连续区域外的核心电路。核心电路耦合到至少一个连接位置。

13. 发明授权

US08918669B2 Mesochronous signaling system with clock-stopped low power mode 有权
标题翻译：具有时钟停止低功耗模式的中间信号系统
公开(公告)号：US08918669B2
公开(公告)日：2014-12-23
申请号：US13132094
申请日：2009-07-09
申请人： Frederick A. Ware , Robert E. Palmer , John W. Poulton , Andrew M. Fuller
发明人： Frederick A. Ware , Robert E. Palmer , John W. Poulton , Andrew M. Fuller
IPC分类号： G06F1/04 , G06F1/08 , G11C7/22 , G11C7/10 , G11C11/4076 , G11C7/04 , G11C11/4096 , G06F13/16
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路装置包括开环时钟分配电路和发射电路，其协作以实现不受源同步定时参考而不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

14. 发明申请

US20140159961A1 LOW-COST TRACKING SYSTEM 有权
标题翻译：低成本跟踪系统
公开(公告)号：US20140159961A1
公开(公告)日：2014-06-12
申请号：US14234623
申请日：2012-08-03
申请人： Frederick A. Ware , Farshid Aryanfar , John Brooks
发明人： Frederick A. Ware , Farshid Aryanfar , John Brooks
IPC分类号： G01S5/02
CPC分类号： G01S13/84 , A63F13/216 , G01S5/0294 , G01S5/06 , G01S7/52004 , G01S13/878 , G01S2007/4091
摘要： A method of tracking a second electronic device with respect to a first electronic device is disclosed. The method includes transmitting a first waveform of a first frequency along a first fixed path associated with the first device. A second waveform having a frequency based on the first frequency is wirelessly transmitted from the first device to the second device along a first wireless path. The second waveform is wirelessly transmitted from the second device to the first device along a second wireless path. The first and second waveforms are received at the phase comparator circuit. A first phase relationship of the received first waveform is then compared to a second phase relationship of the received re-transmitted waveform. A coordinate of the second device is determined with respect to a reference coordinate based on the comparing.
摘要翻译：公开了一种相对于第一电子设备跟踪第二电子设备的方法。该方法包括沿着与第一设备相关联的第一固定路径发送第一频率的第一波形。具有基于第一频率的频率的第二波形沿着第一无线路径从第一设备无线地发送到第二设备。第二波形沿着第二无线路径从第二设备无线发送到第一设备。第一和第二波形在相位比较器电路处被接收。然后将接收的第一波形的第一相位关系与所接收的重发波形的第二相位关系进行比较。基于比较，相对于参考坐标确定第二装置的坐标。

15. 发明申请

US20140003131A1 MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE 有权
标题翻译：包括集成电路存储器件的多字段寻址模式存储器系统
公开(公告)号：US20140003131A1
公开(公告)日：2014-01-02
申请号：US13860825
申请日：2013-04-11
申请人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
发明人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
IPC分类号： G11C8/10
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。第一和第二多个存储单元可以从该接口同时访问。

16. 发明申请

US20130321022A1 METHODS AND APPARATUS FOR TESTING INACCESSIBLE INTERFACE CIRCUITS IN A SEMICONDUCTOR DEVICE 有权
标题翻译：用于测试半导体器件中不可接受的接口电路的方法和装置
公开(公告)号：US20130321022A1
公开(公告)日：2013-12-05
申请号：US13985364
申请日：2012-03-14
申请人： Frederick A. Ware
发明人： Frederick A. Ware
IPC分类号： G01R31/26 , H03L7/00
CPC分类号： G01R31/2882 , G01R31/2607 , G01R31/31726 , G11C29/022 , G11C29/12015 , G11C29/16 , G11C29/50012 , G11C2029/0401 , H03L7/00
摘要： A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.
摘要翻译：半导体IC器件包括用于传送定时信号的定时电路，所述定时电路被配置为接收第一测试信号并且响应于所述第一测试信号而在定时信号中产生延迟，所述第一测试信号包括第一定时事件。所述半导体IC器件还包括接口电路，其被配置为响应于所述定时信号传送所述数据信号，所述接口电路还被配置为接收第二测试信号并响应于所述第二测试信号而实现所述数据信号的延迟所述第二测试信号包括根据测试标准与所述第一定时事件相关的第二定时事件。

17. 发明申请

US20130305074A1 PROTOCOL FOR MEMORY POWER-MODE CONTROL 有权
公开(公告)号：US20130305074A1
公开(公告)日：2013-11-14
申请号：US13980826
申请日：2012-02-15
申请人： Wayne F. Ellis , Wayne S. Richardson , Akash Bansal , Frederick A. Ware , Lawrence Lai , Kishore Ven Kasamsetty
发明人： Wayne F. Ellis , Wayne S. Richardson , Akash Bansal , Frederick A. Ware , Lawrence Lai , Kishore Ven Kasamsetty
IPC分类号： G06F1/32
CPC分类号： G11C11/40615 , G06F1/3234 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C29/022 , G11C29/028
摘要： In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

18. 发明授权

US08560797B2 Method and apparatus for indicating mask information 有权
标题翻译：用于指示掩模信息的方法和装置
公开(公告)号：US08560797B2
公开(公告)日：2013-10-15
申请号：US13421701
申请日：2012-03-15
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasborro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasborro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.
摘要翻译：一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括一个接口，用于在第一组多条引线上向DRAM发送一个第一代码，以指示第一个数据要写入DRAM，列地址以指示要写入第一数据的DRAM中的存储器核的列位置。该接口还用于发送第二代码以指示是否将第一数据的掩码信息发送到DRAM。如果第二代码指示将发送掩码信息，则在发送第二代码之后发送列地址的一部分和掩码信息的一部分。接口进一步通过与第一多个电线分开的第二多个电线将DRAM发送到第一数据。

19. 发明授权

US08537601B2 Memory controller with selective data transmission delay 有权
标题翻译：具有选择性数据传输延迟的存储控制器
公开(公告)号：US08537601B2
公开(公告)日：2013-09-17
申请号：US13543779
申请日：2012-07-06
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C11/24
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A DRAM controller component generates a timing signal and transmits, to a DRAM, write data that requires a first time interval to propagate from the DRAM controller component to the DRAM and to be sampled by the DRAM on one or more edges of the timing signal, a clock signal that requires a second time interval to propagate from the DRAM controller component to the DRAM, and a write command, associated with the write data, to be sampled by the DRAM on one or more edges of the clock signal. The DRAM controller component includes series-coupled delay elements to generate respective incrementally delayed signals, and a multiplexer to select one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval.
摘要翻译： DRAM控制器部件产生定时信号，并且向DRAM发送需要第一时间间隔从DRAM控制器部件传播到DRAM并由DRAM在定时信号的一个或多个边缘进行采样的写入数据，需要第二时间间隔从DRAM控制器部件传播到DRAM的时钟信号以及与写入数据相关联的写入命令，以由DRAM在时钟信号的一个或多个边缘上采样。 DRAM控制器组件包括串联耦合的延迟元件以产生相应的递增延迟的信号，以及多路复用器，用于选择延迟信号中的一个来对写入数据进行传输，以便写入数据的传输基于第一时间间隔和第二时间间隔。

20. 发明申请

US20130208818A1 MEMORY COMPONENTS AND CONTROLLERS THAT UTILIZE MULTIPHASE SYNCHRONOUS TIMING REFERENCES 有权
标题翻译：使用多相同步时序参考的记忆组件和控制器
公开(公告)号：US20130208818A1
公开(公告)日：2013-08-15
申请号：US13823866
申请日：2011-11-19
申请人： Ian Shaeffer , Frederick A. Ware , Scott C. Best
发明人： Ian Shaeffer , Frederick A. Ware , Scott C. Best
IPC分类号： H04L25/40
CPC分类号： H04L25/40 , G06F13/00 , G06F13/1689 , G11C7/22 , Y02D10/14
摘要： Multiple timing reference signals (e.g., clock signals) each cycling at the same frequency are distributed in a fly-by topology to a plurality of memory devices in various embodiments are presented. These multiple clock signals each have a different phase relationship to each other (e.g., quadrature). A first circuit receives a first of these clocks as a first timing reference signal. A second circuit receives a second of these clocks as a second timing reference signal. A plurality of receiver circuits receive signals synchronously with respect to the first timing reference signal and the second timing reference signal, such that a first signal value is resolved using the first timing reference signal and a second signal value is resolved using the second timing reference signal.
摘要翻译：呈现了在各种实施例中以相同频率循环的多个定时参考信号（例如，时钟信号）以飞越拓扑分布到多个存储器件。这些多个时钟信号各自具有彼此不同的相位关系（例如，正交）。第一电路接收这些时钟中的第一个作为第一定时参考信号。第二电路接收这些时钟中的第二时钟作为第二定时参考信号。多个接收器电路相对于第一定时参考信号和第二定时参考信号同步地接收信号，使得使用第一定时参考信号来解析第一信号值，并且使用第二定时参考信号来解析第二信号值。

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