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1. 发明申请

US20090164677A1 TIMING ADJUSTMENT IN A RECONFIGURABLE SYSTEM 有权
标题翻译：可重构系统中的时序调整
公开(公告)号：US20090164677A1
公开(公告)日：2009-06-25
申请号：US12258680
申请日：2008-10-27
申请人： Frederick A. Ware , Ian Shaeffer , Scott C. Best , Craig E. Hampel
发明人： Frederick A. Ware , Ian Shaeffer , Scott C. Best , Craig E. Hampel
IPC分类号： G06F1/04 , G06F13/00
CPC分类号： G06F13/4243
摘要： This disclosure provides a method for adjusting system timing in a reconfigurable memory system. In a Dynamic Point-to-Point (“DPP”) system, for example, manufacturer-supplied system timing parameters such as access latency and maximum clock speed typically reflect a worst-case configuration scenario. By in-situ detecting actual configuration (e.g., whether expansion boards have been inserted), and correspondingly configuring the system to operate in a mode geared to the specific configuration, worst-case or near worst-case scenarios may be ruled out and system timing parameters may be redefined for faster-than-conventionally-rated performance; this is especially the case in a DPP system where signal pathways typically become more direct as additional modules are added. Contrary to convention wisdom therefore, which might dictate that component expansion should slow down timing, clock speed can actually be increased in such a system, if supported by the configuration, for better performance.
摘要翻译：本公开提供了一种用于在可重构存储器系统中调整系统定时的方法。在动态点对点（“DPP”）系统中，例如，制造商提供的系统定时参数，例如访问延迟和最大时钟速度通常反映最坏情况的配置方案。通过原位检测实际配置（例如，是否插入了扩展板），并且相应地将系统配置为以特定配置的方式运行，可能排除最坏情况或接近最坏情况的情况，系统时序可以重新定义参数以达到比常规级别更高的性能; DPP系统尤其如此，其中信号路径通常随着附加模块的添加而变得更直接。因此，与惯例智慧相反，这可能决定组件扩展应该减慢时序，如果配置支持，这样的系统实际上可以增加时钟速度，以获得更好的性能。

2. 发明授权

US08842492B2 Memory components and controllers that utilize multiphase synchronous timing references 有权
标题翻译：使用多相同步定时参考的存储器组件和控制器
公开(公告)号：US08842492B2
公开(公告)日：2014-09-23
申请号：US13823866
申请日：2011-11-19
申请人： Ian Shaeffer , Frederick A. Ware , Scott C. Best
发明人： Ian Shaeffer , Frederick A. Ware , Scott C. Best
IPC分类号： G11C8/00 , H04L25/40 , G06F13/00 , G11C7/22
CPC分类号： H04L25/40 , G06F13/00 , G06F13/1689 , G11C7/22 , Y02D10/14
摘要： Multiple timing reference signals (e.g., clock signals) each cycling at the same frequency are distributed in a fly-by topology to a plurality of memory devices in various embodiments are presented. These multiple clock signals each have a different phase relationship to each other (e.g., quadrature). A first circuit receives a first of these clocks as a first timing reference signal. A second circuit receives a second of these clocks as a second timing reference signal. A plurality of receiver circuits receive signals synchronously with respect to the first timing reference signal and the second timing reference signal, such that a first signal value is resolved using the first timing reference signal and a second signal value is resolved using the second timing reference signal.
摘要翻译：呈现了在各种实施例中以相同频率循环的多个定时参考信号（例如，时钟信号）以飞越拓扑分布到多个存储器件。这些多个时钟信号各自具有彼此不同的相位关系（例如，正交）。第一电路接收这些时钟中的第一个作为第一定时参考信号。第二电路接收这些时钟中的第二时钟作为第二定时参考信号。多个接收器电路相对于第一定时参考信号和第二定时参考信号同步地接收信号，使得使用第一定时参考信号来解析第一信号值，并且使用第二定时参考信号来解析第二信号值。

3. 发明申请

US20130208818A1 MEMORY COMPONENTS AND CONTROLLERS THAT UTILIZE MULTIPHASE SYNCHRONOUS TIMING REFERENCES 有权
标题翻译：使用多相同步时序参考的记忆组件和控制器
公开(公告)号：US20130208818A1
公开(公告)日：2013-08-15
申请号：US13823866
申请日：2011-11-19
申请人： Ian Shaeffer , Frederick A. Ware , Scott C. Best
发明人： Ian Shaeffer , Frederick A. Ware , Scott C. Best
IPC分类号： H04L25/40
CPC分类号： H04L25/40 , G06F13/00 , G06F13/1689 , G11C7/22 , Y02D10/14
摘要： Multiple timing reference signals (e.g., clock signals) each cycling at the same frequency are distributed in a fly-by topology to a plurality of memory devices in various embodiments are presented. These multiple clock signals each have a different phase relationship to each other (e.g., quadrature). A first circuit receives a first of these clocks as a first timing reference signal. A second circuit receives a second of these clocks as a second timing reference signal. A plurality of receiver circuits receive signals synchronously with respect to the first timing reference signal and the second timing reference signal, such that a first signal value is resolved using the first timing reference signal and a second signal value is resolved using the second timing reference signal.
摘要翻译：呈现了在各种实施例中以相同频率循环的多个定时参考信号（例如，时钟信号）以飞越拓扑分布到多个存储器件。这些多个时钟信号各自具有彼此不同的相位关系（例如，正交）。第一电路接收这些时钟中的第一个作为第一定时参考信号。第二电路接收这些时钟中的第二时钟作为第二定时参考信号。多个接收器电路相对于第一定时参考信号和第二定时参考信号同步地接收信号，使得使用第一定时参考信号来解析第一信号值，并且使用第二定时参考信号来解析第二信号值。

4. 发明授权

US08195907B2 Timing adjustment in a reconfigurable system 有权
标题翻译：可重构系统中的时序调整
公开(公告)号：US08195907B2
公开(公告)日：2012-06-05
申请号：US12258680
申请日：2008-10-27
申请人： Frederick A. Ware , Ian Shaeffer , Scott C. Best , Craig E. Hampel
发明人： Frederick A. Ware , Ian Shaeffer , Scott C. Best , Craig E. Hampel
IPC分类号： G06F1/08 , G06F13/16
CPC分类号： G06F13/4243
摘要： This disclosure provides a method for adjusting system timing in a reconfigurable memory system. In a Dynamic Point-to-Point (“DPP”) system, for example, manufacturer-supplied system timing parameters such as access latency and maximum clock speed typically reflect a worst-case configuration scenario. By in-situ detecting actual configuration (e.g., whether expansion boards have been inserted), and correspondingly configuring the system to operate in a mode geared to the specific configuration, worst-case or near worst-case scenarios may be ruled out and system timing parameters may be redefined for faster-than-conventionally-rated performance; this is especially the case in a DPP system where signal pathways typically become more direct as additional modules are added. Contrary to convention wisdom therefore, which might dictate that component expansion should slow down timing, clock speed can actually be increased in such a system, if supported by the configuration, for better performance.
摘要翻译：本公开提供了一种用于在可重构存储器系统中调整系统定时的方法。在动态点对点（“DPP”）系统中，例如，制造商提供的系统定时参数，例如访问延迟和最大时钟速度通常反映最坏情况的配置方案。通过原位检测实际配置（例如，是否插入了扩展板），并且相应地将系统配置为以特定配置的方式运行，可能排除最坏情况或接近最坏情况的情况，系统时序可以重新定义参数以达到比常规级别更高的性能; DPP系统尤其如此，其中信号路径通常随着附加模块的添加而变得更直接。因此，与惯例智慧相反，这可能决定组件扩展应该减慢时序，如果配置支持，这样的系统实际上可以增加时钟速度，以获得更好的性能。

5. 发明申请

US20130227183A1 MEMORY ACCESS DURING MEMORY CALIBRATION 有权
标题翻译：存储器校验期间的存储器访问
公开(公告)号：US20130227183A1
公开(公告)日：2013-08-29
申请号：US13883542
申请日：2011-11-07
申请人： Ian Shaeffer , Frederick A. Ware
发明人： Ian Shaeffer , Frederick A. Ware
IPC分类号： G06F13/16
CPC分类号： G06F12/1458 , G06F12/023 , G06F13/16 , G06F13/1657 , G06F13/1684 , G06F13/1694 , G06F2212/1044 , G06F2212/1052
摘要： A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.
摘要翻译：一种多级存储器系统，其中在存储器控制器和一级存储器之间执行校准操作，同时数据在控制器和其他等级的存储器之间传送。存储器控制器执行校准操作，其校准与存储器控制器和存储器的第一等级中的存储器件之间经由第一数据总线的数据传输有关的参数。当控制器执行校准操作时，控制器还经由第二数据总线将存储器件中的数据与第二等级的存储器传送数据。

6. 发明授权

US09176903B2 Memory access during memory calibration 有权
标题翻译：存储器校准过程中的存储器访问
公开(公告)号：US09176903B2
公开(公告)日：2015-11-03
申请号：US13883542
申请日：2011-11-07
申请人： Ian Shaeffer , Frederick A. Ware
发明人： Ian Shaeffer , Frederick A. Ware
IPC分类号： G06F13/16
CPC分类号： G06F12/1458 , G06F12/023 , G06F13/16 , G06F13/1657 , G06F13/1684 , G06F13/1694 , G06F2212/1044 , G06F2212/1052
摘要： A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.
摘要翻译：一种多级存储器系统，其中在存储器控制器和一级存储器之间执行校准操作，同时数据在控制器和其他等级的存储器之间传送。存储器控制器执行校准操作，其校准与存储器控制器和存储器的第一等级中的存储器件之间经由第一数据总线的数据传输有关的参数。当控制器执行校准操作时，控制器还经由第二数据总线将存储器件中的数据与第二等级的存储器传送数据。

7. 发明申请

US20100180143A1 TECHNIQUES FOR IMPROVED TIMING CONTROL OF MEMORY DEVICES 审中-公开
标题翻译：改进记忆设备时序控制的技术
公开(公告)号：US20100180143A1
公开(公告)日：2010-07-15
申请号：US12596360
申请日：2008-04-14
申请人： Frederick A. Ware , Carl Werner , Ian Shaeffer
发明人： Frederick A. Ware , Carl Werner , Ian Shaeffer
IPC分类号： G06F1/04 , G11C7/00 , G06F12/00
CPC分类号： G11C8/18 , G11C29/02 , G11C29/023 , G11C29/028
摘要： Techniques for improved timing control of memory devices are disclosed. In one embodiment, the techniques may be realized as a memory controller to communicate with a memory device via a communications link. The memory controller may comprise a memory interface to exchange data with the memory device via a set of N conductors according to at least one clock, the data being encoded such that each M bits of data are represented by at least one symbol and each symbol is associated with a combination of signal levels on a group of n conductors, wherein M
摘要翻译：公开了用于改进存储器件定时控制的技术。在一个实施例中，这些技术可以被实现为存储器控制器，以经由通信链路与存储器设备进行通信。存储器控制器可以包括存储器接口，用于根据至少一个时钟经由一组N个导体与存储器件交换数据，该数据被编码，使得每个M位的数据由至少一个符号表示，并且每个符号是与一组n导体上的信号电平的组合相关联，其中M

8. 发明授权

US09330735B2 Memory with deferred fractional row activation 有权
$Memory with deferred fractional row activation$
标题翻译：具有延迟分数行激活的内存
公开(公告)号：US09330735B2
公开(公告)日：2016-05-03
申请号：US13640084
申请日：2012-06-08
申请人： James Edward Harris , Thomas Vogelsang , Frederick A. Ware , Ian P. Shaeffer
发明人： James Edward Harris , Thomas Vogelsang , Frederick A. Ware , Ian P. Shaeffer
IPC分类号： G11C7/00 , G11C7/06 , G11C5/02 , G11C7/10 , G11C11/4076 , G11C11/408 , G11C11/4091 , G11C7/08
CPC分类号： G11C7/1039 , G11C5/025 , G11C7/06 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/222 , G11C8/08 , G11C8/10 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the sub-row to be activated.
摘要翻译：存储器组件内的行激活操作相对于子行执行，而不是完整的存储行，以减少功耗。此外，除了响应于行命令激活子代以外，子代激活操作被延迟，直到接收到指定要执行的列操作的列命令和要被激活的子行。

9. 发明授权

US09287239B2 Techniques for interconnecting stacked dies using connection sites 有权
标题翻译：使用连接点互连堆叠管芯的技术
公开(公告)号：US09287239B2
公开(公告)日：2016-03-15
申请号：US13641680
申请日：2011-04-13
申请人： Frederick A. Ware , Ely Tsern , Thomas Vogelsang
发明人： Frederick A. Ware , Ely Tsern , Thomas Vogelsang
IPC分类号： H01L25/16 , H01L23/538 , H01L25/065 , H01L25/18 , H01L23/48
CPC分类号： H01L23/481 , G06F3/0604 , G06F3/0629 , G06F3/0673 , G06F2213/0038 , H01L25/0657 , H01L25/18 , H01L2224/131 , H01L2224/16146 , H01L2225/06544 , H01L2924/014
摘要： An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.
摘要翻译：集成电路管芯包括至少位于其连续区域内的集成电路管芯的表面上的导电连接位置。集成电路还包括位于连续区域外的核心电路。核心电路耦合到至少一个连接位置。

10. 发明授权

US08918669B2 Mesochronous signaling system with clock-stopped low power mode 有权
标题翻译：具有时钟停止低功耗模式的中间信号系统
公开(公告)号：US08918669B2
公开(公告)日：2014-12-23
申请号：US13132094
申请日：2009-07-09
申请人： Frederick A. Ware , Robert E. Palmer , John W. Poulton , Andrew M. Fuller
发明人： Frederick A. Ware , Robert E. Palmer , John W. Poulton , Andrew M. Fuller
IPC分类号： G06F1/04 , G06F1/08 , G11C7/22 , G11C7/10 , G11C11/4076 , G11C7/04 , G11C11/4096 , G06F13/16
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路装置包括开环时钟分配电路和发射电路，其协作以实现不受源同步定时参考而不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

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