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11. 发明授权

US07071539B2 Chemical planarization performance for copper/low-k interconnect structures 有权
公开(公告)号：US07071539B2
公开(公告)日：2006-07-04
申请号：US10628925
申请日：2003-07-28
申请人： Lee M Nicholson , Wei-Tsu Tseng , Christy S Tyberg
发明人： Lee M Nicholson , Wei-Tsu Tseng , Christy S Tyberg
IPC分类号： H01L23/58 , H01L23/48
CPC分类号： H01L23/5329 , H01L21/76807 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/7684 , H01L21/7688 , H01L2924/0002 , Y10T428/31663 , H01L2924/00
摘要： An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

12. 发明授权

US07008871B2 Selective capping of copper wiring 有权
标题翻译：铜线选择性封盖
公开(公告)号：US07008871B2
公开(公告)日：2006-03-07
申请号：US10611931
申请日：2003-07-03
申请人： Panayotis C. Andricacos , Shyng-Tsong Chen , John M. Cotte , Hariklia Deligianni , Mahadevaiyer Krishnan , Wei-Tsu Tseng , Philippe M. Vereecken
发明人： Panayotis C. Andricacos , Shyng-Tsong Chen , John M. Cotte , Hariklia Deligianni , Mahadevaiyer Krishnan , Wei-Tsu Tseng , Philippe M. Vereecken
IPC分类号： H01L21/44
CPC分类号： H01L21/76846 , H01L21/2885 , H01L21/6708 , H01L21/76849 , H01L21/7685 , H01L21/76874 , H01L21/76883
摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.
摘要翻译：通过在衬垫材料的存在下使用选择性蚀刻和/或选择性电镀选择性地封盖铜来制造图案化的铜结构。提供了用于解决在电蚀和/或电镀过程中作为电解质增加的电阻路径从晶片边缘向内流动的问题的装置。

13. 发明授权

US6165886A Advanced IC bonding pad design for preventing stress induced passivation cracking and pad delimitation through stress bumper pattern and dielectric pin-on effect 有权
标题翻译：先进的IC焊盘设计，用于通过应力保险杠图案和介电引脚效应防止应力诱发的钝化裂纹和焊盘定界
公开(公告)号：US6165886A
公开(公告)日：2000-12-26
申请号：US193298
申请日：1998-11-17
申请人： Chi-Fa Lin , Wei-Tsu Tseng , Min-Shinn Feng
发明人： Chi-Fa Lin , Wei-Tsu Tseng , Min-Shinn Feng
IPC分类号： H01L21/60 , H01L23/485 , H01L21/44
CPC分类号： H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48724 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/351 , H01L2924/00014 , H01L2924/00
摘要： An improved metal bonding pad is disclosed which can prevent the formation of cracks during the high temperature PECVD deposition, and the subsequent annealing, of a passivation layer which is formed to encroach the metal bonding pad and provide an encapsulation force on the metal bonding pad. The metal bonding pad comprises a plurality of stress bumpers on the periphery thereof. The stress bumpers can be hollow elongated round-cornered rectangles, pin-shaped circles, Y-shaped polygons, or ellipses. The stress bumpers, which create a discontinuous structure in the metal pad, can effectively stop stress propagation as well as relieve and re-direct stress propagation, so as to maintain the integrity of the passivation encroachment and prevent the peeling off problems often observed with the metal bonding pad.
摘要翻译：公开了一种改进的金属焊盘，其可以防止在高温PECVD沉积期间形成裂纹，以及随后退火形成为钝化金属焊盘并在金属焊盘上提供封装力的钝化层。金属焊盘包括在其周边上的多个应力缓冲器。应力缓冲器可以是中空的长圆形矩形矩形，销状圆形，Y形多边形或椭圆形。在金属垫中产生不连续结构的应力缓冲器可以有效地阻止应力传播以及缓解并重新引导应力传播，从而保持钝化侵入的完整性，并防止剥离常见于金属焊盘。

14. 发明申请

US20130063173A1 METHOD OF REPAIRING PROBE PADS 有权
标题翻译：修复探针垫的方法
公开(公告)号：US20130063173A1
公开(公告)日：2013-03-14
申请号：US13615368
申请日：2012-09-13
申请人： John H. Zhang , Laertis Economikos , Robin Van Den Nieuwenhuizen , Wei-Tsu Tseng
发明人： John H. Zhang , Laertis Economikos , Robin Van Den Nieuwenhuizen , Wei-Tsu Tseng
IPC分类号： G01R1/04
CPC分类号： H01L22/20 , H01L22/14 , H01L24/05 , H01L2924/014 , H01L2924/14 , H01L2924/00
摘要： A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.
摘要翻译：一种方法，其包括在衬底上形成第一电平的有源电路，形成电连接到所述第一电平有源电路的第一探针焊盘，其中所述第一探针焊盘具有第一表面，所述第一探针焊盘与所述第一探针焊盘接触，所述第一探针焊盘的位于所述第一表面上方的部分，以及在所述第一探针焊盘上执行化学机械抛光，以在所述第一表面上方平坦化所述第一探针焊盘的所述部分。该方法还包括形成覆盖在第一探针焊盘上的第二电平有源电路，形成电连接到第二电平有源电路的第二探针焊盘，使第二探针焊盘与移位探针焊盘的一部分的探针尖接触，以及化学机械地抛光第二探针垫以除去所移动的部分。

15. 发明申请

US20110156032A1 METHOD OF REPAIRING PROBE PADS 有权
标题翻译：修复探针垫的方法
公开(公告)号：US20110156032A1
公开(公告)日：2011-06-30
申请号：US12651332
申请日：2009-12-31
申请人： John H. Zhang , Laertis Economikos , Robin Van Den Nieuwenhuizen , Wei-Tsu Tseng
发明人： John H. Zhang , Laertis Economikos , Robin Van Den Nieuwenhuizen , Wei-Tsu Tseng
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L22/20 , H01L22/14 , H01L24/05 , H01L2924/014 , H01L2924/14 , H01L2924/00
摘要： A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.
摘要翻译：一种方法，其包括在衬底上形成第一电平的有源电路，形成电连接到所述第一电平有源电路的第一探针焊盘，其中所述第一探针焊盘具有第一表面，所述第一探针焊盘与所述第一探针焊盘接触，所述第一探针焊盘的位于所述第一表面上方的部分，以及在所述第一探针焊盘上执行化学机械抛光，以在所述第一表面上方平坦化所述第一探针焊盘的所述部分。该方法还包括形成覆盖在第一探针焊盘上的第二电平有源电路，形成电连接到第二电平有源电路的第二探针焊盘，使第二探针焊盘与移位探针焊盘的一部分的探针尖接触，以及化学机械地抛光第二探针垫以除去所移动的部分。

16. 发明申请

US20060166012A1 Chemical planarization performance for copper/low-k interconnect structures 有权
标题翻译：铜/低k互连结构的化学平面化性能
公开(公告)号：US20060166012A1
公开(公告)日：2006-07-27
申请号：US11369476
申请日：2006-03-07
申请人： Lee Nicholson , Wei-Tsu Tseng , Christy Tyberg
发明人： Lee Nicholson , Wei-Tsu Tseng , Christy Tyberg
IPC分类号： B32B9/04
CPC分类号： H01L23/5329 , H01L21/76807 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/7684 , H01L21/7688 , H01L2924/0002 , Y10T428/31663 , H01L2924/00
摘要： An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.
摘要翻译：在基板上的电互连结构，其包括：第一低k电介质层; 共价键合到第一低k电介质层的自旋低k CMP保护层; 并提供CVD沉积的硬掩模/ CMP抛光停止层。可以在第一低k电介质层中形成电通孔和线。旋转低k CMP保护层可防止由于中心到边缘或不同金属密度区域的CMP工艺中的不均匀性而导致的低k电介质的损坏。可以调节低k CMP保护层的厚度以适应CMP工艺中的较大变化，而不显着影响结构的有效介电常数。

17. 发明申请

US20050001325A1 Selective capping of copper wiring 有权
标题翻译：铜线选择性封盖
公开(公告)号：US20050001325A1
公开(公告)日：2005-01-06
申请号：US10611931
申请日：2003-07-03
申请人： Panayotis Andricacos , Shyng-Tsong Chen , John Cotte , Hariklia Deligianni , Mahadevaiyer Krishnan , Wei-Tsu Tseng , Philippe Vereecken
发明人： Panayotis Andricacos , Shyng-Tsong Chen , John Cotte , Hariklia Deligianni , Mahadevaiyer Krishnan , Wei-Tsu Tseng , Philippe Vereecken
IPC分类号： H01L21/00 , H01L21/288 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76846 , H01L21/2885 , H01L21/6708 , H01L21/76849 , H01L21/7685 , H01L21/76874 , H01L21/76883
摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.
摘要翻译：通过在衬垫材料的存在下使用选择性蚀刻和/或选择性电镀选择性地封盖铜来制造图案化的铜结构。提供了用于解决在电蚀和/或电镀过程中作为电解质增加的电阻路径从晶片边缘向内流动的问题的装置。

18. 发明授权

US5922091A Chemical mechanical polishing slurry for metallic thin film 失效
标题翻译：用于金属薄膜的化学机械抛光浆料
公开(公告)号：US5922091A
公开(公告)日：1999-07-13
申请号：US857846
申请日：1997-05-16
申请人： Ming-Shih Tsai , Wei-Tsu Tseng
发明人： Ming-Shih Tsai , Wei-Tsu Tseng
IPC分类号： C09G1/02 , C09K3/14 , B24D3/34
CPC分类号： C09G1/02 , C09K3/1463
摘要： This invention provides metallic thin film chemical mechanical polishing slurry compositions having improved suspension stability. The slurry contains 2.5-10% by weight of alumina powder and 2-20% by volume of phosphoric acid (80% concentration ) solution, and using potassium hydroxide to adjust its pH to 1-6 so as to increase suspension ability of the alumina powder in the aqueous slurry. The polishing slurry compositions can further combine with suitable oxidizers such as hydrogen peroxide, ferric nitrate and so on to be appropriately used for chemical mechanical polishing metallic thin film in the process of manufacturing semiconductor in order to control abrasion rate and unevenness more easily.
摘要翻译：本发明提供具有改进的悬浮稳定性的金属薄膜化学机械抛光浆料组合物。该浆料含有2.5-10重量％的氧化铝粉末和2-20体积％的磷酸（80％浓度）溶液，并且使用氢氧化钾将其pH调节至1-6，以提高氧化铝的悬浮能力粉末在水性浆液中。抛光浆料组合物可以进一步与合适的氧化剂如过氧化氢，硝酸铁等组合，以在半导体制造过程中适用于化学机械抛光金属薄膜，以更容易地控制磨损率和不均匀性。

19. 发明授权

US09607864B2 Dual medium filter for ion and particle filtering during semiconductor processing 有权
公开(公告)号：US09607864B2
公开(公告)日：2017-03-28
申请号：US13479087
申请日：2012-05-23
申请人： John H. Zhang , Laertis Economikos , Wei-Tsu Tseng , Adam Ticknor
发明人： John H. Zhang , Laertis Economikos , Wei-Tsu Tseng , Adam Ticknor
IPC分类号： H01L21/02 , H01L21/67 , B01D24/00 , B01D53/82
CPC分类号： H01L21/67017 , B01D15/362 , B01D15/363 , B01D24/002 , B01D24/008 , B01D53/82 , B01D2201/287 , B01D2221/14 , B01D2253/206 , B01D2258/0216 , H01L21/6704 , H01L21/67051
摘要： The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as to a semiconductor wafer cleaning tool.

20. 发明授权

US08822994B2 Method of repairing probe pads 有权
标题翻译：修复探针垫的方法
公开(公告)号：US08822994B2
公开(公告)日：2014-09-02
申请号：US13615368
申请日：2012-09-13
申请人： John H. Zhang , Laertis Economikos , Robin Van Den Nieuwenhuizen , Wei-Tsu Tseng
发明人： John H. Zhang , Laertis Economikos , Robin Van Den Nieuwenhuizen , Wei-Tsu Tseng
IPC分类号： H01L23/58 , H01L29/10 , H01L21/66
CPC分类号： H01L22/20 , H01L22/14 , H01L24/05 , H01L2924/014 , H01L2924/14 , H01L2924/00
摘要： A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.
摘要翻译：一种方法，其包括在衬底上形成第一电平的有源电路，形成电连接到所述第一电平有源电路的第一探针焊盘，其中所述第一探针焊盘具有第一表面，所述第一探针焊盘与所述第一探针焊盘接触，所述第一探针焊盘的位于所述第一表面上方的部分，以及在所述第一探针焊盘上执行化学机械抛光，以在所述第一表面上方平坦化所述第一探针焊盘的所述部分。该方法还包括形成覆盖在第一探针焊盘上的第二电平有源电路，形成电连接到第二电平有源电路的第二探针焊盘，使第二探针焊盘与移位探针焊盘的一部分的探针尖接触，以及化学机械地抛光第二探针垫以除去所移动的部分。

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