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11. 发明授权

US06587931B1 Directory-based cache coherency system supporting multiple instruction processor and input/output caches 失效
标题翻译：基于目录的高速缓存一致性系统支持多指令处理器和输入/输出缓存
公开(公告)号：US06587931B1
公开(公告)日：2003-07-01
申请号：US09001598
申请日：1997-12-31
申请人： Mitchell A. Bauman , Eugene A. Rodi , Douglas E. Morrissey
发明人： Mitchell A. Bauman , Eugene A. Rodi , Douglas E. Morrissey
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F12/0886 , G06F2212/621
摘要： A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/O) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line. The cache line states are used to implement a state machine which tracks the cache lines and ensures only valid copies of are maintained within the memory system. According to another aspect of the system, the main memory performs continuous tracking and control functions for all cache lines residing in the IP caches. In contrast, the system maintains tracking and control functions for only predetermined cache lines provided to the I/O units so that system overhead may be reduced. The coherency system further supports multiple heterogeneous instruction processors which operate on cache lines of different sizes.
摘要翻译：公开了一种基于目录的高速缓存一致性系统，用于具有通过共享主存储器耦合的多个指令处理器（IP）和多个输入/输出（I / O）单元的数据处理系统。该系统包括一个或多个IP高速缓冲存储器，每个IP缓存存储器分别耦合到一个或多个IP和共享主存储器，用于高速缓存被称为高速缓存线的数据单元。该系统还包括一个或多个I / O单元内的I / O存储器，每个I / O存储器耦合到共享主存储器，用于存储从共享主存储器检索的高速缓存线。通过使用存储系统中每个缓存行的状态的中央目录来维护一致性。该状态表示IP高速缓存和具有给定高速缓存行的有效副本的I / O存储器的身份，并进一步标识与高速缓存行相关联的一组访问权限，即高速缓存行“状态”。高速缓存行状态用于实现跟踪高速缓存行的状态机，并且仅确保在存储器系统内维护的有效副本。根据系统的另一方面，主存储器对驻留在IP高速缓存中的所有高速缓存行执行连续跟踪和控制功能。相比之下，系统仅为提供给I / O单元的预定高速缓存行维护跟踪和控制功能，从而可以减少系统开销。一致性系统还支持在不同大小的高速缓存线上运行的多个异构指令处理器。

12. 发明授权

US06263409B1 Data processing system and method for substituting one type of request for another for increased performance when processing back-to-back requests of certain types 失效
标题翻译：数据处理系统和方法，用于在处理某些类型的背对背请求时，将一种类型的请求替换为另一种请求以提高性能
公开(公告)号：US06263409B1
公开(公告)日：2001-07-17
申请号：US09218383
申请日：1998-12-22
申请人： Michael L. Haupt , Eugene A. Rodi
发明人： Michael L. Haupt , Eugene A. Rodi
IPC分类号： G06F1314
CPC分类号： G06F13/1626 , G06F12/0817
摘要： A data processing system and method for substituting selected requests with substitute requests that perform the same or similar end function but achieve increased system performance are disclosed. Those requests that have a selected request characteristic are identified and converted or replaced with a predetermined substitute request. The substitute requests perform at least part of the function of the identified requests. The data processing system may include two or more processors, and the selected request characteristic may be that a write data packet of an identified write request was not changed by a first processor. A substitute request may update directory information associated with the identified write request but may not write to associated data packet to memory. The directory information can indicate whether identified memory locations are currently owned by a processor. The substitute request may also send the associated write data packet from the first processor to a second processor via a processor-to-processor interface. It may be determined whether a processor block has changed selected data by examining a function code of a write type request.
摘要翻译：公开了一种使用执行相同或相似的终端功能但实现增加的系统性能的替代请求替换所选择的请求的数据处理系统和方法。具有选定请求特征的请求被识别并转换或替换为预定的替代请求。替代请求执行所识别的请求的至少一部分功能。数据处理系统可以包括两个或多个处理器，并且所选择的请求特性可以是所识别的写入请求的写入数据分组没有被第一处理器改变。替代请求可以更新与所识别的写入请求相关联的目录信息，但是可能不向相关联的数据分组写入存储器。目录信息可以指示所识别的存储器位置当前是否由处理器拥有。替代请求还可以经由处理器到处理器接口将相关联的写入数据包从第一处理器发送到第二处理器。可以通过检查写入类型请求的功能代码来确定处理器块是否已经改变了所选择的数据。

13. 发明授权

US5649092A Fault tolerant apparatus and method for maintaining one or more queues that are shared by multiple processors 失效
标题翻译：用于维护由多个处理器共享的一个或多个队列的容错装置和方法
公开(公告)号：US5649092A
公开(公告)日：1997-07-15
申请号：US583765
申请日：1996-01-11
申请人： Ferris T. Price, deceased , Eugene A. Rodi , Marvin W. Theis
发明人： Ferris T. Price, deceased , Eugene A. Rodi , Marvin W. Theis
IPC分类号： G06F11/14 , G06F13/00
CPC分类号： G06F11/2043 , G06F11/203 , G06F11/2035
摘要： The disclosure relates to a high performance fault tolerant queuing system. Multiple processors share access to one or more queues which are stored in an addressable memory. A storage controller provides general access to the addressable memory and includes queue functions for maintaining the queues. Queue access is provided in a first-come/first-served basis. In addition to the get and put queue functions, queue control within the storage control saves a queue item which is read from the queue in a location in the addressable memory which is associated with the processor making a get request, thereby alleviating the requesting processor from having to save the queue item.
摘要翻译：本公开涉及高性能容错排队系统。多个处理器共享访问存储在可寻址存储器中的一个或多个队列。存储控制器提供对可寻址存储器的一般访问，并且包括用于维护队列的队列功能。队列访问以先到先得的方式提供。除了获取和放置队列功能之外，存储控制器内的队列控制还保存了一个队列项目，该队列项目可从与队列相关联的可寻址存储器中的一个位置从队列中读取，从而缓解请求处理器必须保存队列项。

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