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    • 11. 发明授权
    • Overlay scan line processing
    • 叠加扫描线处理
    • US06999089B1
    • 2006-02-14
    • US09539637
    • 2000-03-30
    • Fong-Shek LamKim A. Meinerth
    • Fong-Shek LamKim A. Meinerth
    • G09G5/397
    • G09G5/395G09G5/14G09G2340/045G09G2340/125
    • An overlay video processing system provides an early start to pixel processing for the next overlay scan line. The overlay processor begins processing the next overlay scan line while still displaying the current scan line. A FIFO buffer is used to provide the overlay video data to the display. When the buffer provides a predetermined amount of data to the current overlay scan line, the buffer begins to load the data for the next overlay scan line. In one embodiment, the buffer may begin loading data for the next overlay scan line when approximately half the current overlay scan line is displayed.
    • 覆盖视频处理系统为下一个叠加扫描线提供了早期的像素处理开始。 覆盖处理器开始处理下一个叠加扫描线,同时仍显示当前的扫描线。 FIFO缓冲器用于向显示器提供覆盖视频数据。 当缓冲器向当前覆盖扫描线提供预定量的数据时,缓冲器开始加载下一叠加扫描线的数据。 在一个实施例中,当显示当前叠加扫描线的大约一半时,缓冲器可以开始为下一叠加扫描线加载数据。
    • 13. 发明授权
    • High-throughput interconnect allowing bus transactions based on partial
access requests
    • 高吞吐量互连允许基于部分访问请求的总线事务
    • US5911051A
    • 1999-06-08
    • US721686
    • 1996-09-27
    • David G. CarsonGeorge R. HayekBrent S. BaxterColyn CaseKim A. MeinerthBrian K. Langendorf
    • David G. CarsonGeorge R. HayekBrent S. BaxterColyn CaseKim A. MeinerthBrian K. Langendorf
    • G06F13/16G06F13/14
    • G06F13/1631G06F13/161G06F13/1615
    • A high throughput memory access interface is provided. The interface includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The interface allows memory access requests to be performed in such a manner that only portions of an access request are required to be transmitted to the target device for certain bus transactions. Each access request includes command bits, address bits, and length bits. In the initiating device, each access request is separated into three segments, which are stored in separate registers in both the initiating device and the target device. Only the segment which contains the lowest order address bits and the length bits is required by the target device to initiate the bus transaction. Thus, if either of the other two segments has not changed since the previous access request, then such segment or segments are not transmitted to the target. If such segment or segments have changed since the previous access request, then they are provided to the target only for purposes of updating state in the target. Access requests may optionally be provided to the target on a separate port from the port used to transmit data in response to access requests.
    • 提供了高吞吐量的存储器访问接口。 该接口包括在系统内存和视频/图形或音频适配器之间提供比使用标准本地总线架构(如PCI或ISA)可能提供更高数据传输速率的功能。 该接口允许以这样的方式执行存储器访问请求,使得只有访问请求的一部分需要被发送到目标设备以用于某些总线事务。 每个访问请求包括命令位,地址位和长度位。 在发起设备中,每个访问请求被分成三个段,它们存储在起始设备和目标设备中的单独的寄存器中。 目标设备只需要包含最低位地址位和长度位的段来启动总线事务。 因此,如果其他两个段中的任何一个从先前的访问请求起没有改变,则这样的段或段不被发送到目标。 如果这些片段或片段自从先前的访问请求以来已经改变,那么它们被提供给目标,仅用于更新目标中的状态。 访问请求可以可选地在与用于响应于访问请求传输数据的端口的单独端口上提供给目标。