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11. 发明授权

US07301108B2 Multi-layered interconnect structure using liquid crystalline polymer dielectric 有权
标题翻译：使用液晶聚合物电介质的多层互连结构
公开(公告)号：US07301108B2
公开(公告)日：2007-11-27
申请号：US10959711
申请日：2004-10-05
申请人： Frank D. Egitto , Donald S. Farquhar , Voya R. Markovich , Mark D. Poliks , Douglas O. Powell
发明人： Frank D. Egitto , Donald S. Farquhar , Voya R. Markovich , Mark D. Poliks , Douglas O. Powell
IPC分类号： H05K1/11 , H01R12/04
CPC分类号： H01L21/4853 , H01L23/3735 , H01L23/49822 , H01L2224/16225 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01068 , H01L2924/01078 , H01L2924/01322 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/462 , H05K3/4623 , H05K3/4626 , H05K3/4632 , H05K3/4641 , H05K3/4688 , H05K2201/0141 , H05K2201/0191 , H05K2201/068 , H05K2201/09509 , H05K2201/09536 , H05K2201/09554 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T156/1092
摘要： A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.
摘要翻译：多层互连结构和形成方法。在第一实施例中，第一和第二液晶聚合物（LCP）电介质层分别直接接合到导热层的第一和第二相对表面，没有外在粘合材料将导热层与第一或第二液晶聚合物 LCP电介质层。在第二实施例中，第一和第二2S1P子结构分别直接接合到LCP电介质接合层的第一和第二相对表面，没有外部粘合材料将LCP电介质接合层与第一或第二2S1P子结构结合。

12. 发明授权

US07084509B2 Electronic package with filled blinds vias 有权
标题翻译：带盲孔通孔的电子包装
公开(公告)号：US07084509B2
公开(公告)日：2006-08-01
申请号：US10263909
申请日：2002-10-03
申请人： Frank D. Egitto , Elizabeth Foster , Raymond T. Galasco , Voya R. Markovich , Manh-Quan Tam Nguyen
发明人： Frank D. Egitto , Elizabeth Foster , Raymond T. Galasco , Voya R. Markovich , Manh-Quan Tam Nguyen
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H05K1/115 , H01L21/486 , H01L23/49827 , H01L2924/0002 , H05K3/4602 , H05K2201/09509 , H05K2201/09554 , H05K2201/096 , H05K2203/0733 , H01L2924/00
摘要： The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.
摘要翻译：通过在层叠到用作接地平面或电源平面的导电金属芯的第一介电层中提供盲目的无地通孔来改善电子封装的密度和利用堆叠盲孔的子组件的电可靠性。通过延伸到芯的电介质层提供孔。使用金属芯作为阴极电解沉积诸如铜的金属，或者无电渗入孔中。金属沉积在芯上并逐渐建立在孔中以达到通孔所需的深度。第二电介质层被层压到第一电介质层，并且具有与第一通孔对准的第二层盲孔。该第二通孔可以由常规电镀技术形成。可以以这种方式组装具有堆叠的盲孔的多个电介质层。

13. 发明授权

US06881072B2 Membrane probe with anchored elements 失效
公开(公告)号：US06881072B2
公开(公告)日：2005-04-19
申请号：US10263510
申请日：2002-10-01
申请人： Frank D. Egitto , Keith J. Miller , Manh-Quan T. Nguyen
发明人： Frank D. Egitto , Keith J. Miller , Manh-Quan T. Nguyen
IPC分类号： G01R1/067 , G01R1/073 , H05K3/20 , H05K3/40 , H05K3/42 , H01R12/00
CPC分类号： G01R1/06733 , G01R1/0735 , H01R12/52 , H01R12/7082 , H01R12/714 , H01R2201/20 , H05K3/205 , H05K3/4007 , H05K3/423 , H05K2201/0367 , H05K2201/09745 , H05K2201/09845 , H05K2201/10378 , H05K2203/0369 , H05K2203/0733 , Y10T29/4922
摘要： A structure and method to establish an electrical connection between a tester and an electrical component. A flexible dielectric layer has a first side and a second side. A through via extends through the first side and the second side of the dielectric layer. A blind via is placed in a position that is offset from the through via and extends laterally in a first direction from a section of the first through via to a section of the flexible dielectric layer. The blind via extends in a second direction from the first side of the flexible dielectric layer to a section of the flexible dielectric layer that is between the first side and the second side of the dielectric layer. An electrically conductive member extends through the through via and extends into the blind via, thereby filling the through via and the blind via. The electrically conductive member has a first surface and a second surface. Any distance between the first surface and the second surface is greater than a distance between the first side of the dielectric layer and the second side of the dielectric layer.

14. 发明授权

US06790305B2 Method and structure for small pitch z-axis electrical interconnections 失效
标题翻译：小间距z轴电气互连的方法和结构
公开(公告)号：US06790305B2
公开(公告)日：2004-09-14
申请号：US10266652
申请日：2002-10-08
申请人： Brian E. Curcio , Frank D. Egitto , Robert M. Japp , Thomas R. Miller , Manh-Quan T. Nguyen , Douglas O. Powell
发明人： Brian E. Curcio , Frank D. Egitto , Robert M. Japp , Thomas R. Miller , Manh-Quan T. Nguyen , Douglas O. Powell
IPC分类号： B32B3114
CPC分类号： H01L21/486 , H05K3/4069 , H05K3/4614 , H05K3/462 , H05K2201/09536 , H05K2201/096 , H05K2203/0191 , H05K2203/0264 , H05K2203/061 , H05K2203/1152 , Y10S438/976 , Y10T29/49165 , Y10T428/24917 , Y10T428/28 , Y10T428/2804 , Y10T428/2839 , Y10T428/2848
摘要： A method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. A method for parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.
摘要翻译：一种用于在印刷电路板和各种电子封装上施加介电材料层的小间距z轴电互连的方法。一种用于平行制造中间结构的方法，其随后连接以形成最终结构。此外，提供了一种采用诸如树脂涂覆铜之类的介电材料的z互连电结构，可用于制造包括印刷线路板（PWB），基板，多芯片模块等的各种类型的电子封装。

15. 发明授权

US06719871B2 Method for bonding heat sinks to overmolds and device formed thereby 有权
公开(公告)号：US06719871B2
公开(公告)日：2004-04-13
申请号：US09757185
申请日：2001-01-09
申请人： Frank D. Egitto , Michael A. Gaynes , Ramesh R. Kodnani , Luis J. Matienzo , Mark V. Pierson
发明人： Frank D. Egitto , Michael A. Gaynes , Ramesh R. Kodnani , Luis J. Matienzo , Mark V. Pierson
IPC分类号： B32B3114
CPC分类号： B29C59/14 , H01L21/56 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2924/15311 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： A method for bonding heat sinks to packaged electronic components comprises the steps of: (a) exposing to a plasma a surface of a molded polymer formed on a substrate; (b) allowing the plasma to at least partially convert silicon-containing residue on the surface to silica; and (c) bonding an article to the surface by applying an adherent between the article and the surface. Often, the silicon-containing residue is silicone oil, a mold release compound, which may prevent the formation of a bond when using conventional bonding methods and materials. The silica layer formed on the surface of the molded polymer assists in formation of a proper bond. The plasma may be an oxygen plasma and the adherent may be selected from either a heat cured silicone-based paste adhesive with a metal oxide filler or a heat cured porous polymer film impregnated with adhesive. In particular, the film may be polytetrafluoroethylene, the adhesive may be polybutadine, and the film may be further impregnated with a metal oxide heat transfer medium, such as zinc oxide. An alternate method comprises applying the porous polymer film without plasma treatment and heat curing the film to form a proper bond.

16. 发明授权

US06607613B2 Solder ball with chemically and mechanically enhanced surface properties 失效
标题翻译：焊球具有化学和机械增强的表面性能
公开(公告)号：US06607613B2
公开(公告)日：2003-08-19
申请号：US09775747
申请日：2001-02-01
申请人： Frank D. Egitto , Edmond O. Fey , Luis J. Matienzo , David L. Questad , Rajinder S. Rai , Daniel C. Van Hart
发明人： Frank D. Egitto , Edmond O. Fey , Luis J. Matienzo , David L. Questad , Rajinder S. Rai , Daniel C. Van Hart
IPC分类号： C22C1106
CPC分类号： C23C8/00 , B23K1/206 , B23K35/0244 , B23K35/262 , B23K35/268 , B23K2101/40 , C23C26/00 , H05K3/3457 , H05K3/3489 , H05K2203/092 , H05K2203/095 , Y10T428/12 , Y10T428/12021 , Y10T428/12458 , Y10T428/12493 , Y10T428/12687
摘要： A metal alloy solder ball comprising a first metal and a second metal, the first metal having a sputtering yield greater than the second metal. The solder ball comprises a bulk portion having a bulk ratio of the first metal to the second metal, an outer surface, and a surface gradient having a depth and a gradient ratio of the first metal to the second metal that is less than the bulk ratio. The gradient ratio increases along the surface gradient depth from a minimum at the outer surface. The solder ball may be formed by the process of exposing the ball to energized ions of a sputtering gas for an effective amount of time to form the surface gradient.
摘要翻译：一种包含第一金属和第二金属的金属合金焊球，所述第一金属的溅射产率大于所述第二金属。焊球包括具有第一金属与第二金属的体积比的主体部分，外表面和具有小于体积比的第一金属与第二金属的深度和梯度比的表面梯度。梯度比沿着表面梯度深度从外表面的最小值增加。可以通过将球暴露于溅射气体的激发离子有效时间以形成表面梯度的过程来形成焊球。

17. 发明授权

US06509546B1 Laser excision of laminate chip carriers 失效
标题翻译：激光切割层压芯片载体
公开(公告)号：US06509546B1
公开(公告)日：2003-01-21
申请号：US09526034
申请日：2000-03-15
申请人： Frank D. Egitto , John S. Kresge
发明人： Frank D. Egitto , John S. Kresge
IPC分类号： B23K2618
CPC分类号： H05K3/0038 , B23K26/40 , B23K2101/34 , B23K2103/02 , B23K2103/05 , B23K2103/08 , B23K2103/10 , B23K2103/12 , B23K2103/172 , B23K2103/42 , B23K2103/50 , H01L21/78 , H05K1/056 , H05K3/0052 , H05K3/44 , H05K2201/09036 , H05K2201/0909
摘要： A method and associated structure for excising laminate chip carriers from a panel that has a thickness less than about 100 mils. A laser beam is focused on a surface of the panel, and the panel is moved relative to the laser beam in a geometric pattern, such that cells of the panel (e.g., chip carriers) are excised from the panel. The laser parameters include a wavelength between about 500 nanometers and about 600 nanometers, a pulse width greater than about 100 nanoseconds and less than about 350 nanoseconds, an average power of at least about 1 watt, a pulse repetition rate between about 5,000 pulses/sec and about 20,000 pulses/sec, and a target diameter (D) between about 2 microns and about 30 microns. The kerf width between adjacent excised cells is between about 2 microns and about 75 microns. The width of an excised cell is at least 5 mm. A displacement between successive pulses of the laser beam is less than about 2D. The panel may comprise a layered structure that includes an organic layer and a metal layer. The laser includes, inter alia, a lasant of Nd:YAG, Nd:YLF, Nd:YAP, or Nd:YVO4. The method of the present invention wastes less panel area by at least a factor of about 13 than does the mechanical excising techniques of the related art.
摘要翻译：一种用于从厚度小于约100密耳的面板切割层压芯片载体的方法和相关结构。激光束聚焦在面板的表面上，并且面板以几何图案相对于激光束移动，使得面板的单元（例如，芯片载体）从面板上被切除。激光参数包括约500纳米至约600纳米之间的波长，大于约100纳秒且小于约350纳秒的脉冲宽度，至少约1瓦特的平均功率，约5,000脉冲/秒之间的脉冲重复率和约20,000脉冲/秒，目标直径（D）在约2微米至约30微米之间。相邻切割细胞之间的切口宽度在约2微米至约75微米之间。切除的细胞的宽度至少为5mm。激光束的连续脉冲之间的位移小于约2D。面板可以包括层状结构，其包括有机层和金属层。激光器尤其包括Nd：YAG，Nd：YLF，Nd：YAP或Nd：YVO4的农民。与现有技术的机械切除技术相比，本发明的方法比面板面积少了约13倍。

18. 发明授权

US5194713A Removal of excimer laser debris using carbon dioxide laser 失效
标题翻译：使用二氧化碳激光去除准分子激光碎片
公开(公告)号：US5194713A
公开(公告)日：1993-03-16
申请号：US777057
申请日：1991-10-17
申请人： Frank D. Egitto , Cynthia J. Moring , Daniel C. Van Hart
发明人： Frank D. Egitto , Cynthia J. Moring , Daniel C. Van Hart
IPC分类号： H01L21/48 , H05K1/03 , H05K3/00
CPC分类号： H05K3/0032 , H01L21/486 , H05K3/0055 , H05K1/0366 , H05K2201/015 , H05K2203/107 , H05K2203/108 , H05K3/0035 , H05K3/0047 , H05K3/005
摘要： Disclosed is a method of fabricating a microelectronic circuit package. The circuit package has a reinforced fluorocarbon polymer dielectric. According to the disclosed process, vias or through holes are formed in the composite by a process that leaves debris. The debris in the formed vias or through holes is reflowed in order to smooth the via and through hole walls for subsequent plating.
摘要翻译：公开了一种制造微电子电路封装的方法。电路封装具有增强的氟碳聚合物电介质。根据所公开的方法，通过留下碎片的方法在复合材料中形成通孔或通孔。形成的通孔或通孔中的碎屑被回流以便平滑通孔和通孔壁用于随后的电镀。

19. 发明授权

US4985112A Enhanced plasma etching 失效
标题翻译：增强等离子体蚀刻
公开(公告)号：US4985112A
公开(公告)日：1991-01-15
申请号：US12696
申请日：1987-02-09
申请人： Frank D. Egitto , Walter E. Mlynko
发明人： Frank D. Egitto , Walter E. Mlynko
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H05K3/00
CPC分类号： H01L21/31138 , H05K3/0017
摘要： Increased etching rates are obtained by plasma etching wherein the power is applied in a cyclical or oscillating mode.

20. 发明授权

US4654115A Process for removing contaminant 失效
标题翻译：去除污染物的方法
公开(公告)号：US4654115A
公开(公告)日：1987-03-31
申请号：US849247
申请日：1986-04-08
申请人： Frank D. Egitto , Francis Emmi , Walter E. Mlynko , Robin A. Susko
发明人： Frank D. Egitto , Francis Emmi , Walter E. Mlynko , Robin A. Susko
IPC分类号： B08B3/08 , H01L21/302 , H01L21/304 , H01L21/3065 , H05K3/00 , H05K3/08 , H05K3/26 , H05K3/42 , B44C1/22 , B29C37/00 , C03C15/00 , C03C25/06
CPC分类号： H05K3/0055 , H05K2203/095
摘要： Contaminant is removed from holes by etching in a gaseous plasma by first removing contaminant from the vicinity of the edges of the hole. Next, a mask is provided in the vicinity of the edges to prevent etching by contacting with a gaseous plasma which is different from the gaseous plasma employed in the first etching step. The holes are then etched in a gaseous plasma to remove contaminant from the interior of the holes in the vicinity of the center of the holes, whereby the mask protects the edges from being etched.
摘要翻译：通过首先从孔的边缘附近去除污染物，通过在气态等离子体中蚀刻从孔中除去污染物。接下来，在边缘附近设置掩模，以防止与不同于在第一蚀刻步骤中使用的气态等离子体接触的气体等离子体进行蚀刻。然后在气体等离子体中蚀刻孔，以从孔的中心附近的孔的内部除去污染物，由此掩模保护边缘不被蚀刻。

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