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11. 发明申请

US20110264979A1 ERROR-CORRECTION DECODER EMPLOYING EXTRINSIC MESSAGE AVERAGING 有权
标题翻译：错误修正解码器使用超级消息平均
公开(公告)号：US20110264979A1
公开(公告)日：2011-10-27
申请号：US12766038
申请日：2010-04-23
申请人： Kiran Gunnam , Shaohua Yang , Changyou Xu
发明人： Kiran Gunnam , Shaohua Yang , Changyou Xu
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/116 , H03M13/09 , H03M13/1128 , H03M13/1137 , H03M13/114 , H03M13/1142 , H03M13/2906 , H03M13/6306
摘要： In one embodiment, an LDPC decoder has a controller and an extrinsic log-likelihood (LLR) value generator. The extrinsic LLR value generator is selectively configurable to operate in either (i) a non-averaging mode that updates extrinsic LLR values without averaging or (ii) an averaging mode that updates extrinsic LLR values using averaging. Initially, the extrinsic LLR value generator is configured to generate non-averaged extrinsic LLR values, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged extrinsic LLR values. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) the extrinsic LLR value generator is configured to generate average extrinsic LLR values, and (iii) the decoder attempts to recover the correct codeword using the average extrinsic LLR values. Averaging the extrinsic LLR values may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets.
摘要翻译：在一个实施例中，LDPC解码器具有控制器和外在对数似然（LLR）值发生器。外部LLR值发生器可选择性地配置为以下操作：（i）不平均更新外在LLR值的非平均模式，或（ii）使用平均更新外在LLR值的平均模式。最初，外部LLR值发生器被配置为产生非平均的外在LLR值，并且解码器尝试使用非平均的外在LLR值来恢复LDPC编码码字。如果解码器不能恢复正确的码字，则（i）控制器选择平均模式，（ii）外部LLR值发生器被配置为产生平均外在LLR值，以及（iii）解码器尝试恢复正确的码字码字使用平均外在LLR值。平衡外部LLR值可能会减慢导致解码器收敛的错误消息的传播。

12. 发明申请

US20110119553A1 SUBWORDS CODING USING DIFFERENT ENCODING/DECODING MATRICES 有权
标题翻译：使用不同的编码/解码矩阵进行子代码编码
公开(公告)号：US20110119553A1
公开(公告)日：2011-05-19
申请号：US12644622
申请日：2009-12-22
申请人： Kiran Gunnam , Yang Han , Shaohua Yang , Changyou Xu
发明人： Kiran Gunnam , Yang Han , Shaohua Yang , Changyou Xu
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/2957 , H03M13/1102 , H03M13/116 , H03M13/27 , H03M13/2757 , H03M13/6331 , H03M13/6343 , H04L1/0041 , H04L1/0057 , H04L1/0071
摘要： In a communications system that demultiplexes user data words into multiple sub-words for encoding and decoding within different subword-processing paths, the minimum distance between bit errors in an extrinsic codeword can be increased by having corresponding subword encoders/decoders in the different subword-processing paths perform subword encoding/decoding with different encoder/decoder matrices.
摘要翻译：在将用户数据字分解为多个子字以在不同的子处理路径内进行编码和解码的通信系统中，可以通过在不同的子字处理路径中具有对应的子字编码器/解码器来增加外部码字中的位错误之间的最小距离，处理路径使用不同的编码器/解码器矩阵执行子字编码/解码。

13. 发明申请

US20100042904A1 BREAKING UNKNOWN TRAPPING SETS USING A DATABASE OF KNOWN TRAPPING SETS 有权
标题翻译：使用已知的跟踪设置的数据库打破未知的跟踪设置
公开(公告)号：US20100042904A1
公开(公告)日：2010-02-18
申请号：US12540002
申请日：2009-08-12
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： H03M13/45 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： In one embodiment, an LDPC decoder attempts to recover an originally-encoded LDPC codeword based on a set of channel soft-output values. If the decoder observes a trapping set, then the decoder compares the observed trapping set to known trapping sets stored in a trapping-set database to determine whether or not the observed trapping set is a known trapping set. If the observed trapping set is not known, then the decoder selects a most-dominant trapping set from the trapping-set database and identifies the locations of erroneous bit nodes in the selected trapping set. Then, the decoder adjusts the channel soft-output values corresponding to the identified erroneous bit nodes. Adjustment is performed by inverting some or all of the hard-decision bits of the corresponding channel soft-output values and setting the confidence value of each corresponding channel soft-output value to maximum. Decoding is then restarted using the adjusted channel soft-output values.
摘要翻译：在一个实施例中，LDPC解码器尝试基于一组信道软输出值来恢复原始编码的LDPC码字。如果解码器观察到捕获集合，则解码器将观察到的捕获集合与存储在捕获集合数据库中的已知捕获集进行比较，以确定观察到的捕获集合是否为已知捕获集合。如果观察到的捕获集合是未知的，则解码器从陷阱集数据库中选择最主要的捕获集合并且识别所选择的捕获集合中的错误位节点的位置。然后，解码器调整对应于所识别的错误位节点的信道软输出值。通过将相应通道软输出值的某些或全部硬判决位反相，并将每个相应通道软输出值的置信度值设置为最大值来执行调整。然后使用调整后的通道软输出值重新开始解码。

14. 发明申请

US20100042902A1 ERROR-FLOOR MITIGATION OF ERROR-CORRECTION CODES BY CHANGING THE DECODER ALPHABET 有权
标题翻译：通过更改解码器字符来错误修正错误代码
公开(公告)号：US20100042902A1
公开(公告)日：2010-02-18
申请号：US12420535
申请日：2009-04-08
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： H03M13/45 , H03M13/05 , G06F11/10 , G06F5/01 , G06F17/10
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： In one embodiment, an LDPC decoder has one or more reconfigurable adders that generate variable-node messages and one or more reconfigurable check-node units (CNUs) that generate check-node messages. The LDPC decoder has a five-bit precision mode in which the reconfigurable adders and CNUs are configured to process five-bit variable-node and check-node messages, respectively. If the LDPC decoder is unable to properly decode codewords in five-bit precision mode, then the decoder can be reconfigured in real time into a ten-bit precision mode in which the reconfigurable adders and CNUs are configured to process ten-bit variable-node and check-node messages, respectively. By increasing the size of the variable-node and check-node messages from five bits to ten bits, the probability that the LDPC decoder will decode the codeword correctly may be increased.
摘要翻译：在一个实施例中，LDPC解码器具有生成可变节点消息的一个或多个可重构加法器和产生校验节点消息的一个或多个可重新配置的校验节点单元（CNU）。 LDPC解码器具有五位精度模式，其中可配置加法器和CNU被配置为分别处理五位可变节点和校验节点消息。如果LDPC解码器不能以五比特精度模式正确地解码码字，则可以将解码器实时重新配置为十位精度模式，其中可配置加法器和CNU被配置为处理十位可变节点和检查节点消息。通过将可变节点和校验节点消息的大小从5比特增加到10比特，可以增加LDPC解码器正确地解码码字的概率。

15. 发明申请

US20100042897A1 SELECTIVELY STRENGTHENING AND WEAKENING CHECK-NODE MESSAGES IN ERROR-CORRECTION DECODERS 有权
标题翻译：在错误修正解码器中选择加强和减弱检查节点信息
公开(公告)号：US20100042897A1
公开(公告)日：2010-02-18
申请号：US12538915
申请日：2009-08-11
申请人： Yang Han , Kiran Gunnam , Shaohua Yang , Hao Zhong , Nils Graef , Yuan Xing Lee
发明人： Yang Han , Kiran Gunnam , Shaohua Yang , Hao Zhong , Nils Graef , Yuan Xing Lee
IPC分类号： H03M13/05 , G06F11/07 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values.
摘要翻译：在一个实施例中，LDPC解码器具有多个校验节点单元（CNU）和控制器。最初，CNU基于由控制器选择的初始偏移值生成校验节点消息。如果解码器收敛于陷阱集合，则控制器为不满意的校验节点（MSC）（其位置近似）和/或不满足的校验节点（USC）选择新的偏移值。特别地，选择偏移值，使得（i）相对于MSC的消息相对于将使用初始偏移值生成的消息减少和/或（ii）相对于USC的消息相对于将使用初始偏移值生成的消息。然后继续解码指定数量的迭代以打破陷阱集。在其他实施例中，控制器选择缩放因子，而不是或附加于偏移值。

16. 发明申请

US20100042893A1 RECONFIGURABLE CYCLIC SHIFTER 有权
标题翻译：可重复循环切换
公开(公告)号：US20100042893A1
公开(公告)日：2010-02-18
申请号：US12492374
申请日：2009-06-26
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： G06F9/318 , H03M13/05 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： In one embodiment, a reconfigurable cyclic shifter is selectively configurable to operate in (i) five-bit mode to cyclically shift N five-bit messages by up to N degrees or (ii) ten-bit mode to cyclically shift N ten-bit messages by up to N degrees. The reconfigurable cyclic shifter has two five-bit N/2-way non-reconfigurable cyclic shifters. The two non-reconfigurable cyclic shifters together, without additional hardware, do not perform N degrees of cyclic shifting. Thus, five-bit and ten-bit reordering hardware is provided that enables the reconfigurable cyclic shifter to perform up to N degrees of cyclic shifting in the five- and ten-bit modes, respectively. In the five-bit mode, the N five-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts N/2 of the N messages. In ten-bit mode, N/2 of the N ten-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts five of the ten bits of each ten-bit message.
摘要翻译：在一个实施例中，可重构的循环移位器被选择性地配置为在（i）五位模式中操作以将N个五位消息循环移位高达N度，或者（ii）十位模式以循环移位N个十位消息最多N度。可重构循环移位器具有两个五位N / 2路不可重构循环移位器。两个不可重新配置的循环移位器在没有附加硬件的情况下一起不执行N度的循环移位。因此，提供了五位和十位重新排序硬件，其使得可重新配置的循环移位器分别在五位和十位模式中执行高达N度的循环移位。在5比特模式中，N个5比特消息被同时移位，其中每个不可重新配置的循环移位器移动N个消息的N / 2。在十比特模式中，N个10比特消息中的N / 2被同时移位，其中每个不可重新配置的循环移位器移动每个十比特消息的十比特中的五个。

17. 发明申请

US20100042891A1 ERROR-CORRECTION DECODER EMPLOYING CHECK-NODE MESSAGE AVERAGING 有权
标题翻译：错误修正解码器使用检查节点消息平均
公开(公告)号：US20100042891A1
公开(公告)日：2010-02-18
申请号：US12475786
申请日：2009-06-01
申请人： Kiran Gunnam , Shaohua Yang , Changyou Xu
发明人： Kiran Gunnam , Shaohua Yang , Changyou Xu
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). Each CNU is selectively configurable to operate in (i) a first mode that updates check-node (i.e., R) messages without averaging and (ii) a second mode that that updates R messages using averaging. Initially, each CNU is configured in the first mode to generate non-averaged R messages, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged R messages. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) each CNU is configured to operate in the second mode to generate averaged R messages, and (iii) the decoder attempts to recover the correct codeword using the averaged R messages. Averaging the R messages may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets.
摘要翻译：在一个实施例中，LDPC解码器具有控制器和一个或多个校验节点单元（CNU）。每个CNU可选择性地配置为在（i）不平均更新校验节点（即，R）消息的第一模式和（ii）使用平均来更新R消息的第二模式。最初，每个CNU被配置为第一模式以产生非平均的R消息，并且解码器尝试使用非平均的R消息来恢复LDPC编码的码字。如果解码器不能恢复正确的码字，则（i）控制器选择平均模式，（ii）每个CNU被配置为在第二模式下操作以产生平均的R消息，并且（iii）解码器尝试恢复使用平均R消息的正确码字。平均R消息可能会减慢导致解码器收敛的错误消息的传播。

18. 发明授权

US08484535B2 Error-floor mitigation of codes using write verification 有权
标题翻译：使用写入验证的错误代码减少代码
公开(公告)号：US08484535B2
公开(公告)日：2013-07-09
申请号：US12994288
申请日：2009-04-21
申请人： Nils Graef , Kiran Gunnam
发明人： Nils Graef , Kiran Gunnam
IPC分类号： G11C29/00
CPC分类号： H03M13/1102 , G06F11/1012 , G11B20/1833 , G11B2020/1823 , G11B2020/185 , G11B2220/2516 , G11B2220/61 , H03M13/1108 , H03M13/1142 , H03M13/455
摘要： Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any erroneous bits, and (iii) stores the erroneous-bit indices to a record in a table. At some later time, the written codeword is read and sent to a decoder. If the decoder fails with a near codeword, a write-error recovery process searches the table and retrieves the erroneous-bit information. The codeword bits at those indices are adjusted, and the modified codeword is submitted to further processing.
摘要翻译：当通道输入（例如，LDPC）码字被写入存储介质时执行，写入验证方法（i）将信道输入码字与写入的码字进行比较，（ii）识别任何错误比特，以及（iii）表中记录的错误位索引。在稍后的时间，写入的码字被读取并发送到解码器。如果解码器出现接近码字失败，则写入错误恢复过程将搜索表并检索错误位信息。调整这些索引处的码字比特，并且修改的码字被提交进一步处理。

19. 发明申请

US20130124590A1 RECONFIGURABLE CYCLIC SHIFTER ARRANGEMENT 有权
标题翻译：可重新安装的循环安装
公开(公告)号：US20130124590A1
公开(公告)日：2013-05-16
申请号：US13294332
申请日：2011-11-11
申请人： Kiran Gunnam , Madhusudan Kalluri
发明人： Kiran Gunnam , Madhusudan Kalluri
IPC分类号： G06F7/00
CPC分类号： G06F5/017
摘要： In one embodiment, a reconfigurable cyclic shifter arrangement has first and second reconfigurable cyclic shifters connected in series that are each selectively and independently configurable to operate in any one of three different modes at a time. In a first mode, the reconfigurable cyclic shifter is configured as four 4×4 cyclic shifters to cyclically shift four sets of four input values. In a second mode, the reconfigurable cyclic shifter is configured as two 8×8 cyclic shifters to cyclically shift two sets of eight input values. In a third mode, the reconfigurable cyclic shifter is configured as one 16×16 cyclic shifter to cyclically shift one set of 16 input values. Because the first and second reconfigurable cyclic shifters are independently configurable, there are nine different configurations of the reconfigurable cyclic shifter arrangement.
摘要翻译：在一个实施例中，可重构循环移位器装置具有串联连接的第一和第二可重构循环移位器，每个可选择性循环移位器可选择性地和独立地配置为一次以三种不同模式中的任何一种运行。在第一模式中，可重构循环移位器被配置为四个4×4循环移位器循环移位四组四个输入值。在第二模式中，可重构循环移位器被配置为两个8×8循环移位器以循环移位两组八个输入值。在第三模式中，可重构循环移位器被配置为一个16×16循环移位器，以循环移位一组16个输入值。因为第一和第二可重构循环移位器是可独立配置的，所以可重构循环移位器装置有九种不同的配置。

20. 发明授权

US08402348B1 Systems and methods for variable data processing using a central queue 失效
标题翻译：使用中央队列进行可变数据处理的系统和方法
公开(公告)号：US08402348B1
公开(公告)日：2013-03-19
申请号：US12785416
申请日：2010-05-21
申请人： Kiran Gunnam , Shaohua Yang
发明人： Kiran Gunnam , Shaohua Yang
IPC分类号： G11C29/00
CPC分类号： H03M13/27 , G06F11/1008 , H03M13/09 , H03M13/1102 , H03M13/1515 , H03M13/3905 , H03M13/4138 , H03M13/6337 , H03M13/6508
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes two or more detection processing circuits, a decoder processing circuit and a memory. The memory is coupled to both of the data detection processing circuits and the decoder processing circuit. In some instances of the aforementioned embodiments, the system further includes a scheduling circuit that is operable to govern access to the memory by the detection processing circuits and the decoder processing circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括两个或更多个检测处理电路，解码器处理电路和存储器的数据处理系统。存储器耦合到数据检测处理电路和解码器处理电路。在上述实施例的一些情况下，系统还包括调度电路，其可操作以通过检测处理电路和解码器处理电路来控制对存储器的访问。

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