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11. 发明授权

US06727534B1 Electrically programmed MOS transistor source/drain series resistance 有权
标题翻译：电子编程MOS晶体管源极/漏极串联电阻
公开(公告)号：US06727534B1
公开(公告)日：2004-04-27
申请号：US10022847
申请日：2001-12-20
申请人： James F. Buller , Qi Xiang , Derick J. Wristers
发明人： James F. Buller , Qi Xiang , Derick J. Wristers
IPC分类号： H01L2979
CPC分类号： H01L29/4983 , H01L29/42376 , H01L29/66484 , H01L29/6656
摘要： High-speed MOS transistors are provided by forming a conductive layer embedded in transistor gate sidewall spacers. The embedded conductive layer is electrically insulated from the gate electrode and the source/drain regions of the transistor. The embedded conductive layer is positioned over the source/drain extensions and causes charge to accumulate in the source/drain extensions lowering the series resistance of the source/drain regions.
摘要翻译：通过形成嵌入在晶体管栅极侧壁间隔物中的导电层来提供高速MOS晶体管。嵌入式导电层与晶体管的栅极电极和源极/漏极区域电绝缘。嵌入的导电层位于源极/漏极延伸部分上方，并使电荷累积在源极/漏极延伸部中，从而降低源极/漏极区域的串联电阻。

12. 发明授权

US06589847B1 Tilted counter-doped implant to sharpen halo profile 有权
标题翻译：倾斜反掺杂植入物以锐化晕轮廓
公开(公告)号：US06589847B1
公开(公告)日：2003-07-08
申请号：US09631557
申请日：2000-08-03
申请人： Daniel Kadosh , Scott D. Luning , Derick J. Wristers
发明人： Daniel Kadosh , Scott D. Luning , Derick J. Wristers
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/1045 , H01L29/6656
摘要： The present invention is directed to a method of forming halo implant regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, the substrate being doped with a first type of dopant material, and forming halo implant regions in the substrate adjacent the gate electrode by performing at least the following steps: performing a first angled implant process using a dopant material that is of a type opposite to the first type of dopant material and performing a second angled implant using a dopant material that is of the same type as the first type of dopant material. The method concludes with performing at least one additional implantation process to further form source/drain regions for the device.
摘要翻译：本发明涉及一种在半导体器件中形成卤素注入区的方法。在一个说明性实施例中，该方法包括在半导体衬底之上形成栅电极，该衬底被掺杂有第一种类型的掺杂剂材料，以及通过至少执行以下步骤在邻近栅极的衬底中形成卤素注入区域：执行使用与第一类型的掺杂剂材料相反的类型的掺杂剂材料并使用与第一类型的掺杂剂材料具有相同类型的掺杂剂材料来执行第二成角度的注入的第一成角度注入工艺。该方法的结论是执行至少一个额外的注入工艺以进一步形成器件的源极/漏极区域。

13. 发明授权

US06225151B1 Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion 失效
标题翻译：晶体管源极/漏极区域之下的氮衬垫以延迟掺杂剂扩散
公开(公告)号：US06225151B1
公开(公告)日：2001-05-01
申请号：US08871469
申请日：1997-06-09
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L2122
CPC分类号： H01L29/0847 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/28176 , H01L21/28202 , H01L21/823814 , H01L29/1033 , H01L29/518 , H01L29/66575 , H01L29/6659 , H01L29/66659 , H01L29/7833
摘要： A nitrogen implanted region formed substantially below and substantially adjacent to a source/drain region of an IGFET forms a liner to retard the diffusion of the source/drain dopant atoms during a subsequent heat treatment operation such as an annealing step. The nitrogen liner may be formed by implantation of nitrogen to a given depth before the implantation of source/drain dopant to a lesser depth. Nitrogen may also be introduced into regions of the IGFET channel region beneath the gate electrode for retarding subsequent lateral diffusion of the source/drain dopant. Such nitrogen introduction may be accomplished using one or more angled implantation steps, or may be accomplished by annealing an implanted nitrogen layer formed using a perpendicular implant aligned to the gate electrode. The liner may be formed on the drain side of the IGFET or on both source and drain side, and may be formed under a lightly-doped region or under a heavily-doped region of the drain and/or source. Such a liner is particularly advantageous for boron-doped source/drain regions, and may be combined with N-channel IGFETs formed without such liners.
摘要翻译：基本上在IGFET的源极/漏极区域下方大致相邻地形成的氮注入区域形成衬垫，以在随后的热处理操作（例如退火步骤）期间阻止源极/漏极掺杂剂原子的扩散。可以在将源极/漏极掺杂剂注入较低深度之前通过将氮注入给定深度来形成氮衬垫。也可以将氮气引入到栅电极下面的IGFET沟道区域的区域中，以阻止源极/漏极掺杂剂的随后的横向扩散。可以使用一个或多个成角度的注入步骤来实现这种氮引入，或者可以通过使用与栅电极对准的垂直注入形成的注入氮层退火来实现。衬垫可以形成在IGFET的漏极侧或源极和漏极两侧，并且可以形成在漏极和/或源极的重掺杂区域的轻掺杂区域下方。这种衬垫对于硼掺杂的源极/漏极区域是特别有利的，并且可以与没有这样的衬垫形成的N沟道IGFET组合。

14. 发明授权

US5970311A Method and structure for optimizing the performance of a semiconductor device having dense transistors 失效
标题翻译：用于优化具有致密晶体管的半导体器件的性能的方法和结构
公开(公告)号：US5970311A
公开(公告)日：1999-10-19
申请号：US961980
申请日：1997-10-31
申请人： Jon Cheek , Daniel Kadosh , Derick J. Wristers
发明人： Jon Cheek , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/66 , H01L23/544 , H01L21/00 , G01R31/26
CPC分类号： H01L22/20 , H01L22/34 , H01L2924/0002
摘要： A method and structure for optimizing the performance of a semiconductor device having dense transistors. A method consistent with the present invention includes forming a first test structure on a first substrate portion. The first test structure includes a transistor having a gate electrode formed at a design width and at a first line spacing similar to the line spacing of a dense transistor. One or more electrical properties the transistor of the first test structure is measured. A second test structure is formed on a second substrate portion. The second test structure includes a transistor having a gate electrode formed at the same design width as the transistor of the first test structure and at a second line spacing greater than the first line spacing. One or more electrical properties of the transistor of the second test structure are measured. Using the measured one or more electrical properties, one or more relationships are developed between the measured one or more electrical properties and the transistors at the first line spacing and the second line spacing.
摘要翻译：一种用于优化具有致密晶体管的半导体器件的性能的方法和结构。与本发明一致的方法包括在第一衬底部分上形成第一测试结构。第一测试结构包括晶体管，其晶体管具有以类似于致密晶体管的线间距的设计宽度和第一行间距形成的栅电极。测量第一测试结构的晶体管的一个或多个电特性。在第二基板部分上形成第二测试结构。第二测试结构包括晶体管，其晶体管具有与第一测试结构的晶体管相同的设计宽度并且在大于第一线间距的第二线间距处形成栅电极。测量第二测试结构的晶体管的一个或多个电特性。使用所测量的一个或多个电性能，在所测量的一个或多个电性能和在第一线间距和第二线间距处的晶体管之间形成一个或多个关系。

15. 发明授权

US06689671B1 Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semiconductor substrate 有权
标题翻译：构建在应变半导体衬底上的MOS器件的低温固相外延制造工艺
公开(公告)号：US06689671B1
公开(公告)日：2004-02-10
申请号：US10151946
申请日：2002-05-22
申请人： Bin Yu , Derick J. Wristers
发明人： Bin Yu , Derick J. Wristers
IPC分类号： H01L2120
CPC分类号： H01L29/6659 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/02667 , H01L21/26506 , H01L21/26513 , H01L29/78687
摘要： A method of manufacturing a semiconductor device, comprising steps of: (a) providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice strain; (b) forming a device structure in the semiconductor substrate by a process comprising forming at least one amorphous region in at least one portion of the strained lattice semiconductor layer; and (c) thermal annealing at a minimum temperature sufficient to effect epitaxial re-crystallization of the at least one amorphous region to re-form a strained lattice semiconductor layer having substantially the pre-selected amount of lattice strain, whereby strain relaxation of the strained lattice semiconductor arising from thermal annealing is substantially eliminated or minimized.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：（a）在其上表面提供包括应变晶格半导体层并具有预选量的晶格应变的半导体衬底;（b）在半导体衬底，其包括在应变晶格半导体层的至少一部分中形成至少一个非晶区; 和（c）在足以实现所述至少一个非晶区域的外延再结晶的最小温度下的热退火以重新形成具有基本上预选量的晶格应变的应变晶格半导体层，由此应变松弛基本消除或最小化由热退火产生的晶格半导体。

16. 发明授权

US07253045B1 Selective P-channel VT adjustment in SiGe system for leakage optimization 有权
标题翻译： SiGe系统中的选择性P沟道VT调整用于泄漏优化
公开(公告)号：US07253045B1
公开(公告)日：2007-08-07
申请号：US10889026
申请日：2004-07-13
申请人： Derick J. Wristers , David Wu , Hormuzdiar E. Nariman
发明人： Derick J. Wristers , David Wu , Hormuzdiar E. Nariman
IPC分类号： H01L27/092 , H01L29/786
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054
摘要： A method of manufacturing a semiconductor device includes forming a silicon germanium layer and a N-channel transistor and a P-channel transistor over the silicon germanium layer. A beta ratio of the N-channel transistor to the P-channel transistor is about 1.8 to about 2.2. A semiconductor device is also disclosed.
摘要翻译：制造半导体器件的方法包括在硅锗层上形成硅锗层和N沟道晶体管以及P沟道晶体管。 N沟道晶体管与P沟道晶体管的β比率为约1.8至约2.2。还公开了一种半导体器件。

17. 发明授权

US06979878B1 Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites 失效
标题翻译：隔离结构在隔离槽的顶角处注入硅原子填充空位和间隙位置
公开(公告)号：US06979878B1
公开(公告)日：2005-12-27
申请号：US09217213
申请日：1998-12-21
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/762 , H01L29/36
CPC分类号： H01L21/76237
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted ino regions of the active areas in close proximity to the trench isolation structure.
摘要翻译：一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。该方法包括在半导体衬底上形成电介质掩模层。然后通过掩模层形成开口。在开口内的掩模层的侧壁上形成一对电介质隔离物。然后在电介质间隔物之间的半导体衬底中蚀刻沟槽。然后在沟槽的壁和基底上热生长第一介电层。将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。间隔物的一部分也被去除，使得间隔物的厚度在约0至200埃之间。然后将硅原子和/或势垒原子（例如氮原子）注入非常靠近沟槽隔离结构的有源区的多个区域中。

18. 发明授权

US06876037B2 Fully-depleted SOI device 有权
标题翻译：全耗尽的SOI器件
公开(公告)号：US06876037B2
公开(公告)日：2005-04-05
申请号：US10796731
申请日：2004-03-09
申请人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
发明人： Andy C. Wei , Derick J. Wristers , Mark B. Fuselier
IPC分类号： H01L27/12 , H01L21/336 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L29/78609 , H01L2924/0002 , H01L2924/00
摘要： The present invention is generally directed to a fully-depleted SOI device structure. In one illustrative embodiment, the device comprises first, second and third doped regions formed in the bulk substrate, wherein the dopant concentration level in the doped regions is greater than the dopant concentration in the bulk substrate. The first doped region is substantially aligned with the gate electrode of the device, while the second and third doped regions are vertically spaced apart from the first doped region.
摘要翻译：本发明一般涉及一种完全耗尽的SOI器件结构。在一个说明性实施例中，该器件包括形成在本体衬底中的第一，第二和第三掺杂区域，其中掺杂区域中的掺杂剂浓度水平大于本体衬底中的掺杂剂浓度。第一掺杂区域基本上与器件的栅电极对准，而第二和第三掺杂区域与第一掺杂区域垂直间隔开。

19. 发明授权

US06822260B1 Linewidth measurement structure with embedded scatterometry structure 有权
标题翻译：具有嵌入散射结构的线宽测量结构
公开(公告)号：US06822260B1
公开(公告)日：2004-11-23
申请号：US10298664
申请日：2002-11-19
申请人： Hormuzdiar E. Nariman , Derick J. Wristers
发明人： Hormuzdiar E. Nariman , Derick J. Wristers
IPC分类号： H01L2358
CPC分类号： H01L22/34
摘要： A method of manufacturing a semiconductor device includes depositing a layer over a substrate and etching the layer to form a grating structure, a cross bridge test structure and a line width measurement structure. The grating structure includes a plurality of parallel lines and one of the multiple parallel lines is connected to the line width measurement structure and the cross bridge test structure. A scatterometry test is performed on the grating structure to obtain a line width and this width is compared to a line width calculated using the line width measurement structure. A semiconductor device is also disclosed.
摘要翻译：制造半导体器件的方法包括在衬底上沉积层并蚀刻该层以形成光栅结构，交叉桥测试结构和线宽测量结构。光栅结构包括多条平行线，并且多条平行线之一连接到线宽测量结构和交叉桥测试结构。对光栅结构进行散射测试以获得线宽，并将该宽度与使用线宽测量结构计算的线宽进行比较。还公开了一种半导体器件。

20. 发明授权

US06372587B1 Angled halo implant tailoring using implant mask 有权
标题翻译：使用植入物掩模的角度光晕植入物定制
公开(公告)号：US06372587B1
公开(公告)日：2002-04-16
申请号：US09568069
申请日：2000-05-10
申请人： Jon D. Cheek , Scott D. Luning , Derick J. Wristers
发明人： Jon D. Cheek , Scott D. Luning , Derick J. Wristers
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/66659 , H01L29/7835
摘要： A method is provided for forming a halo implant in a substrate adjacent one side of a structure, the method including forming the structure above a surface of the substrate, the structure having first and second edges and forming a mask defining a region adjacent the structure, the mask having a thickness &tgr; above the surface and having an edge disposed a distance &dgr; from the first edge of the structure. The method also includes implanting the halo implant at an angle &agr; with respect to a direction perpendicular to the surface, wherein the tangent of the angle &agr; is at least the ratio of the distance &dgr; to the thickness &tgr;.
摘要翻译：提供了一种用于在邻近结构的一侧的衬底中形成卤素注入的方法，所述方法包括在所述衬底的表面上方形成所述结构，所述结构具有第一和第二边缘并且形成限定邻近所述结构的区域的掩模，该面具具有厚度＆tgr; 并且具有与结构的第一边缘相距一定距离的边缘。该方法还包括将晕圈植入物相对于垂直于该表面的方向以角度α注入，其中角度α的切线至少为距离δ与厚度的比值。

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