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11. 发明授权

US06436819B1 Nitrogen treatment of a metal nitride/metal stack 有权
标题翻译：金属氮化物/金属堆叠的氮处理
公开(公告)号：US06436819B1
公开(公告)日：2002-08-20
申请号：US09495817
申请日：2000-02-01
申请人： Zhi-Fan Zhang , David Pung , Nitin Khurana , Hong Zhang , Roderick Craig Mosely
发明人： Zhi-Fan Zhang , David Pung , Nitin Khurana , Hong Zhang , Roderick Craig Mosely
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , H01L21/76856 , H01L21/76862
摘要： A method for processing a substrate comprising the formation of a metal nitride/metal stack suitable for use as a barrier/liner for sub-0.18 &mgr;m device fabrication. After a metal nitride layer is deposited upon a metal layer, the metal nitride layer is exposed to a treatment step in a nitrogen-containing environment, e.g., a plasma. The plasma treatment modifies the entire metal nitride layer and a top portion of the underlying metal layer. The plasma adds nitrogen to the top portion of the metal layer, resulting in the formation of a nitrated-metal layer. Aside from reducing the microstructure mismatch across the nitride-metal interface, the plasma treatment also densifies and reduces impurities from the deposited nitride layer. The resulting nitride/metal stack exhibits improved film properties, including enhanced adhesion and barrier characteristics. A composite nitride layer of a desired thickness can also be formed by repeating the deposition and treatment cycles of thinner component nitride layers.
摘要翻译：一种用于处理衬底的方法，包括形成适合用作亚0.18μm器件制造的屏障/衬垫的金属氮化物/金属叠层。在将金属氮化物层沉积在金属层上之后，将金属氮化物层暴露于含氮环境（例如等离子体）中的处理步骤。等离子体处理改变整个金属氮化物层和下面的金属层的顶部。等离子体向金属层的顶部添加氮，导致形成硝化金属层。除了减少跨越氮化物 - 金属界面的微结构失配之外，等离子体处理也使沉积的氮化物层致密化和减少杂质。所得到的氮化物/金属堆叠表现出改进的膜性质，包括增强的粘附性和阻隔特性。也可以通过重复较薄的氮化物层的沉积和处理循环来形成所需厚度的复合氮化物层。

12. 发明授权

US06355560B1 Low temperature integrated metallization process and apparatus 有权
标题翻译：低温一体化金属化工艺及装置
公开(公告)号：US06355560B1
公开(公告)日：2002-03-12
申请号：US09209434
申请日：1998-12-10
申请人： Roderick Craig Mosely , Hong Zhang , Fusen Chen , Ted Guo
发明人： Roderick Craig Mosely , Hong Zhang , Fusen Chen , Ted Guo
IPC分类号： H01L214763
CPC分类号： H01L21/76876 , C23C14/568 , C23C16/54 , H01L21/32051 , H01L21/76843 , H01L21/76877 , H01L21/76879
摘要： The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.
摘要翻译：本发明一般涉及在衬底上提供均匀的台阶覆盖和金属层的平坦化以在半微米应用中形成连续的无空隙接触或通孔的改进方法。在本发明的一个方面中，将耐火层沉积在具有高比例接触或在其上形成的通孔的基底上。然后在低温下将CVD金属层沉积到耐火层上，以提供用于PVD金属的保形润湿层。接下来，在低于金属的熔点温度的温度下，将PVD金属沉积在预先形成的CVD金属层上。所得到的CVD / PVD金属层基本上无空隙。金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，就会发生通孔和触点的金属化，而不会在其上形成氧化物层 CVD Al层。

13. 发明授权

US06207222B1 Dual damascene metallization 失效
标题翻译：双镶嵌金属化
公开(公告)号：US06207222B1
公开(公告)日：2001-03-27
申请号：US09379696
申请日：1999-08-24
申请人： Liang-Yuh Chen , Rong Tao , Ted Guo , Roderick Craig Mosely
发明人： Liang-Yuh Chen , Rong Tao , Ted Guo , Roderick Craig Mosely
IPC分类号： B05D512
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76831 , H01L21/76862 , H01L21/76876 , H01L21/76877
摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.
摘要翻译：本发明通常提供用于形成高度集成的互连件的金属化工艺。更具体地，本发明提供了一种双镶嵌互连模块，其包含沉积在包含双镶嵌通孔和线定义的电介质层的所有暴露表面上的阻挡层。在平坦化之前，使用两种或更多种沉积方法在阻挡层上沉积导电金属以填充通孔和导线的定义。本发明提供了具有比铝更低的电阻率（更大的导电性）和更大的电迁移电阻的铜线，铜线和周围介电材料之间的阻挡层，无空隙的半微米选择性CVD Al通过插塞的优点，并减少了实现这种集成的流程步骤。

14. 发明授权

US6107192A Reactive preclean prior to metallization for sub-quarter micron application 失效
标题翻译：金属化之前的反应性预清洗用于二分之一微米的应用
公开(公告)号：US6107192A
公开(公告)日：2000-08-22
申请号：US746
申请日：1997-12-30
申请人： Suchitra Subrahmanyan , Liang-Yuh Chen , Roderick Craig Mosely
发明人： Suchitra Subrahmanyan , Liang-Yuh Chen , Roderick Craig Mosely
IPC分类号： C23C14/02 , C23C16/02 , H01L21/285 , H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/768 , H01L21/4763
CPC分类号： C23C16/0236 , C23C14/022 , H01L21/02063 , H01L21/76814 , H01L21/76843 , H01L21/76861 , Y10S438/906
摘要： The present invention generally provides a precleaning process prior to metallization for submicron features on substrates. The method includes cleaning the submicron features with radicals from a plasma of a reactive gas such as oxygen, a mixture of CF.sub.4 /O.sub.2, or a mixture of He/NF.sub.3, wherein the plasma is preferably generated by a remote plasma source and the radicals are delivered to a chamber in which the substrate is disposed. Native oxides remaining in the submicron features are preferably reduced in a second step by treatment with radicals from a plasma containing hydrogen. Following the first or both precleaning steps, the features can be filled with metal by available metallization techniques which typically include depositing a barrier/liner layer on exposed dielectric surfaces prior to deposition of aluminum, copper, or tungsten. The precleaning and metallization steps can be conducted on available integrated processing platforms.
摘要翻译：本发明通常在金属化之前提供在衬底上的亚微米特征的预清洗工艺。该方法包括用来自诸如氧的反应性气体的等离子体，CF 4 / O 2或He / NF 3的混合物的混合物的自由基清洗亚微米特征，其中等离子体优选由远程等离子体源产生，并且基团是输送到其中设置基板的室。残留在亚微米特征中的天然氧化物优选通过用含有氢的等离子体进行处理而在第二步骤中还原。在第一或两个预清洗步骤之后，特征可以通过可用的金属化技术用金属填充，其通常包括在沉积铝，铜或钨之前在暴露的电介质表面上沉积阻挡层/衬垫层。预清洗和金属化步骤可以在可用的集成处理平台上进行。

15. 发明授权

US5804046A Thin-film forming apparatus 失效
标题翻译：薄膜成型装置
公开(公告)号：US5804046A
公开(公告)日：1998-09-08
申请号：US269971
申请日：1994-07-01
申请人： Susumu Sawada , Junichi Anan , Yoshitaka Kakutani , Hironori Wada , Fumihiko Yanagawa , Roderick Craig Mosely
发明人： Susumu Sawada , Junichi Anan , Yoshitaka Kakutani , Hironori Wada , Fumihiko Yanagawa , Roderick Craig Mosely
IPC分类号： C23C14/24 , C23C14/34 , C23C14/56 , H01J37/32 , H01J37/34 , H01L21/203 , H01L21/285 , C23C14/04
CPC分类号： H01J37/3447 , C23C14/564 , H01J37/34 , H01J2237/022
摘要： A collimator having a particle getter function, and a thin-film forming apparatus equipped with the collimator disposed between a target and a wafer. The collimator is fabricated by assembling particle getter sheets into a lattice, honeycomb, or other structure having a number of rows of openings and fixing the assembly into a frame. The particle getter sheets refers collectively to sheets and plates to be assembled integrally to provide a surface having excellent particle capturing and holding actions. Typically, the collimator is a lattice assembly of embossed, slitted particle getter sheets. The film deposited on the collimator is kept from peeling off, without deteriorating the collimator performance.
摘要翻译：具有颗粒吸气剂功能的准直仪和配备有设置在靶和晶片之间的准直仪的薄膜形成装置。准直器通过将颗粒吸气片组装成具有多排开口并将组件固定到框架中的格子，蜂窝体或其他结构来制造。颗粒吸气片共同地指的是要整体组装的片材和板，以提供具有优异的颗粒捕获和保持作用的表面。通常，准直器是压花的，切割的颗粒吸气片的格子组件。沉积在准直器上的膜不会剥离，而不会使准直器性能恶化。

16. 发明授权

US08324095B2 Integration of ALD tantalum nitride for copper metallization 有权
标题翻译： ALD氮化钽的集成用于铜金属化
公开(公告)号：US08324095B2
公开(公告)日：2012-12-04
申请号：US12627977
申请日：2009-11-30
申请人： Hua Chung , Nirmalya Maity , Jick Yu , Roderick Craig Mosely , Mei Chang
发明人： Hua Chung , Nirmalya Maity , Jick Yu , Roderick Craig Mosely , Mei Chang
IPC分类号： H01L21/768
CPC分类号： H01L21/28562 , C23C16/34 , C23C16/4411 , C23C16/45504 , C23C16/45508 , C23C16/45512 , C23C16/45525 , C23C16/45544 , C23C16/45563 , C23C16/45582 , H01L21/02063 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865 , H01L21/76871
摘要： A method and apparatus for depositing a tantalum nitride barrier layer is provided for use in an integrated processing tool. The tantalum nitride is deposited by atomic layer deposition. The tantalum nitride is removed from the bottom of features in dielectric layers to reveal the conductive material under the deposited tantalum nitride. Optionally, a tantalum layer may be deposited by physical vapor deposition after the tantalum nitride deposition. Optionally, the tantalum nitride deposition and the tantalum deposition may occur in the same processing chamber.
摘要翻译：提供了一种用于沉积氮化钽阻挡层的方法和装置，用于集成处理工具中。通过原子层沉积来沉积氮化钽。从电介质层中的特征的底部去除氮化钽以露出沉积的氮化钽之下的导电材料。任选地，可以在氮化钽沉积之后通过物理气相沉积来沉积钽层。可选地，氮化钽沉积和钽沉积可以发生在相同的处理室中。

17. 发明授权

US07049226B2 Integration of ALD tantalum nitride for copper metallization 有权
标题翻译： ALD氮化钽的集成用于铜金属化
公开(公告)号：US07049226B2
公开(公告)日：2006-05-23
申请号：US10865042
申请日：2004-06-10
申请人： Hua Chung , Nirmalya Maity , Jick Yu , Roderick Craig Mosely , Mei Chang
发明人： Hua Chung , Nirmalya Maity , Jick Yu , Roderick Craig Mosely , Mei Chang
IPC分类号： H01L21/4763
CPC分类号： H01L21/28562 , C23C16/34 , C23C16/4411 , C23C16/45504 , C23C16/45508 , C23C16/45512 , C23C16/45525 , C23C16/45544 , C23C16/45563 , C23C16/45582 , H01L21/02063 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865 , H01L21/76871
摘要： A method and apparatus for depositing a tantalum nitride barrier layer is provided for use in an integrated processing tool. The tantalum nitride is deposited by atomic layer deposition. The tantalum nitride is removed from the bottom of features in dielectric layers to reveal the conductive material under the deposited tantalum nitride. Optionally, a tantalum layer may be deposited by physical vapor deposition after the tantalum nitride deposition. Optionally, the tantalum nitride deposition and the tantalum deposition may occur in the same processing chamber.
摘要翻译：提供了一种用于沉积氮化钽阻挡层的方法和装置，用于集成处理工具中。通过原子层沉积来沉积氮化钽。从电介质层中的特征的底部去除氮化钽以露出沉积的氮化钽之下的导电材料。任选地，可以在氮化钽沉积之后通过物理气相沉积来沉积钽层。可选地，氮化钽沉积和钽沉积可以发生在相同的处理室中。

18. 发明授权

US06905965B2 Reactive preclean prior to metallization for sub-quarter micron application 失效
标题翻译：金属化之前的反应性预清洗用于二分之一微米的应用
公开(公告)号：US06905965B2
公开(公告)日：2005-06-14
申请号：US10780105
申请日：2004-02-17
申请人： Suchitra Subrahmanyan , Liang-Yuh Chen , Roderick Craig Mosely
发明人： Suchitra Subrahmanyan , Liang-Yuh Chen , Roderick Craig Mosely
IPC分类号： C23C14/02 , C23C16/02 , H01L21/285 , H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/768 , H01L21/44
CPC分类号： C23C16/0236 , C23C14/022 , H01L21/02063 , H01L21/76814 , H01L21/76843 , H01L21/76861 , Y10S438/906
摘要： The present invention generally provides a precleaning process prior to metallization for submicron features on substrates. The method includes cleaning the submicron features with radicals from a plasma of a reactive gas such as oxygen, a mixture of CF4/O2, or a mixture of He/NF3, wherein the plasma is preferably generated by a remote plasma source and the radicals are delivered to a chamber in which the substrate is disposed. Native oxides remaining in the submicron features are preferably reduced in a second step by treatment with radicals from a plasma containing hydrogen. Following the first or both precleaning steps, the features can be filled with metal by available metallization techniques which typically include depositing a barrier/liner layer on exposed dielectric surfaces prior to deposition of aluminum, copper, or tungsten. The precleaning and metallization steps can be conducted on available integrated processing platforms.
摘要翻译：本发明通常在金属化之前提供在衬底上的亚微米特征的预清洗工艺。该方法包括用来自反应气体的等离子体（例如氧气），CF 3/4 O 2 / O 2混合物或He / NF混合物的自由基清洗亚微米特征其中等离子体优选地由远程等离子体源产生，并且自由基被输送到其中设置衬底的室。残留在亚微米特征中的天然氧化物优选通过用含有氢的等离子体进行处理而在第二步骤中还原。在第一或两个预清洗步骤之后，特征可以通过可用的金属化技术用金属填充，其通常包括在沉积铝，铜或钨之前在暴露的电介质表面上沉积阻挡层/衬垫层。预清洗和金属化步骤可以在可用的集成处理平台上进行。

19. 发明授权

US06726776B1 Low temperature integrated metallization process and apparatus 有权
标题翻译：低温一体化金属化工艺及装置
公开(公告)号：US06726776B1
公开(公告)日：2004-04-27
申请号：US09370599
申请日：1999-08-09
申请人： Roderick Craig Mosely , Hong Zhang , Fusen Chen , Ted Guo
发明人： Roderick Craig Mosely , Hong Zhang , Fusen Chen , Ted Guo
IPC分类号： C23C1600
CPC分类号： H01L21/76843 , H01L21/76876 , H01L21/76877 , Y10S414/139
摘要： The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.
摘要翻译：本发明一般涉及在衬底上提供均匀的台阶覆盖和金属层的平坦化以在半微米应用中形成连续的无空隙接触或通孔的改进方法。在本发明的一个方面中，将耐火层沉积在具有高比例接触或在其上形成的通孔的基底上。然后在低温下将CVD金属层沉积到耐火层上，以提供用于PVD金属的保形润湿层。接下来，在低于金属的熔点温度的温度下，将PVD金属沉积在预先形成的CVD金属层上。所得到的CVD / PVD金属层基本上无空隙。金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，就会发生通孔和触点的金属化，而不会在其上形成氧化物层 CVD Al层。

20. 发明授权

US6139905A Integrated CVD/PVD Al planarization using ultra-thin nucleation layers 失效
标题翻译：使用超薄成核层的集成CVD / PVD Al平面化
公开(公告)号：US6139905A
公开(公告)日：2000-10-31
申请号：US838839
申请日：1997-04-11
申请人： Liang-Yuh Chen , Mehul Naik , Ted Guo , Roderick Craig Mosely
发明人： Liang-Yuh Chen , Mehul Naik , Ted Guo , Roderick Craig Mosely
IPC分类号： H01L21/28 , H01L21/203 , H01L21/3205 , H01L21/768 , B05D5/12
CPC分类号： H01L21/28556 , H01J37/32082 , H01L21/288 , H01L21/76843 , H01L21/76871 , H01L21/76876 , H01L21/76877
摘要： The present invention provides a method and apparatus for forming an interconnect with application in small feature sizes (such as quarter micron widths) having high aspect ratios. Generally, the present invention provides a method and apparatus for depositing a wetting layer for subsequent physical vapor deposition to fill the interconnect. In one aspect of the invention, the wetting layer is a metal layer deposited using either CVD techniques or electroplating, such as CVD aluminum (Al). The wetting layer is nucleated using an ultra-thin layer, denoted as .di-elect cons. layer, as a nucleation layer. The .di-elect cons. layer is preferably comprised of a material such as Ti, TiN, Al, Ti/TiN, Ta, TaN, Cu, a flush of TDMAT or the like. The .di-elect cons. layer may be deposited using PVD or CVD techniques, preferably PVD techniques to improve film quality and orientation within the feature. Contrary to conventional wisdom, the .di-elect cons. layer is not continuous to nucleate the growth of the CVD wetting layer thereon. A PVD deposited metal is then deposited on the wetting layer at low temperature to fill the interconnect.
摘要翻译：本发明提供一种用于形成具有高纵横比的小特征尺寸（例如四分之一微米宽度）的互连的方法和装置。通常，本发明提供了一种用于沉积用于后续物理气相沉积以润湿互连的润湿层的方法和装置。在本发明的一个方面，润湿层是使用CVD技术或电镀（诸如CVD铝（Al））沉积的金属层。润湿层使用表示为+531层的超薄层作为成核层成核。 +531层优选由诸如Ti，TiN，Al，Ti / TiN，Ta，TaN，Cu的材料，TDMAT等的齐平构成。可以使用PVD或CVD技术沉积+531层，优选PVD技术以改善特征内的膜质量和取向。与常规智慧相反，+531层不连续以使其上的CVD润湿层的生长成核。然后在低温下将PVD沉积的金属沉积在润湿层上以填充互连。

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