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11. 发明申请

US20120117666A1 MULTILAYER SECURING STRUCTURE AND METHOD THEREOF FOR THE PROTECTION OF CRYPTOGRAPHIC KEYS AND CODE 有权
标题翻译：多层保护结构及其保护色谱和代码的方法
公开(公告)号：US20120117666A1
公开(公告)日：2012-05-10
申请号：US13382814
申请日：2010-04-13
申请人： Stefano S. Oggioni , Vincenzo Condorelli , Claudius Feger
发明人： Stefano S. Oggioni , Vincenzo Condorelli , Claudius Feger
IPC分类号： G06F21/00
CPC分类号： G06F21/87 , G06F2221/2107 , G06F2221/2131 , H01L23/576 , H01L2224/16225 , Y10S257/922
摘要： An arrangement for the protection of cryptographic keys and codes from being compromised by external tampering, wherein the arrangement is utilized within a multilayered securing structure. More particularly, there is provided a multilayered securing structure for the protection of cryptographic keys and codes, which may be subject to potential tampering when employed in computers and/or telecommunication systems. A method is provided for producing such multilayered securing structures within a modular substrate with the intent to protect cryptographic keys and codes which are employed in computers and/or telecommunication systems from the dangers of potential tampering or unauthorized access.
摘要翻译：用于保护加密密钥和代码免受外部篡改损害的布置，其中该布置在多层固定结构内使用。更具体地，提供了一种用于保护加密密钥和代码的多层固定结构，当在计算机和/或电信系统中使用密钥和密码时，可能会受到潜在的篡改。提供了一种用于在模块化基板内制造这种多层固定结构的方法，其目的是保护在计算机和/或电信系统中使用的加密密钥和代码免受潜在篡改或未授权访问的危险。

12. 发明授权

US07981849B2 Reversible thermal thickening grease 有权
标题翻译：可逆热增稠润滑脂
公开(公告)号：US07981849B2
公开(公告)日：2011-07-19
申请号：US11683825
申请日：2007-03-08
申请人： Claudius Feger , Jeffrey D. Gelorme , Sushumna Iruvanti , Rajneesh Kumar , Ijeoma M. Nnebe
发明人： Claudius Feger , Jeffrey D. Gelorme , Sushumna Iruvanti , Rajneesh Kumar , Ijeoma M. Nnebe
IPC分类号： C10M145/24 , C10M145/22 , C10M145/14 , C10M143/00 , C10M125/04 , C10M125/10 , C10M125/20
CPC分类号： H01L23/3737 , C10M169/02 , C10M171/02 , C10M2201/0413 , C10M2201/053 , C10M2201/0613 , C10M2201/0623 , C10M2201/1006 , C10M2201/1023 , C10M2203/1025 , C10M2203/1045 , C10M2205/02 , C10M2205/04 , C10M2207/401 , C10M2209/084 , C10M2209/102 , C10M2209/103 , C10M2209/1033 , C10M2211/083 , C10M2217/044 , C10M2229/02 , C10M2229/025 , C10N2220/00 , C10N2220/082 , C10N2220/084 , C10N2220/086 , C10N2230/00 , C10N2230/02 , C10N2230/08 , C10N2240/20 , C10N2250/18 , H01L2924/0002 , H01L2924/00
摘要： A reversible thermal thickening grease for microelectronic packages, in which the grease contains filler particles; at least one polymer; and a binder; in which the filler particles are dispersed within the binder, in which one or more segments of the at least one polymer may be attached to the filler particles prior to dispersion in the binder, and in which the polymer collapses at temperatures below a Theta temperature and swells at temperatures above a Theta temperature. During the operation of a microelectronic package, grease pump-out and air proliferation are minimized with use of the reversible thermal thickening grease, while grease fluidity is retained under repetitive thermal stresses.
摘要翻译：用于微电子封装的可逆热增稠润滑脂，其中润滑脂含有填料颗粒; 至少一种聚合物; 和粘合剂; 其中所述填料颗粒分散在所述粘合剂内，其中所述至少一种聚合物的一个或多个链段可以在分散在所述粘合剂中之前附着到所述填料颗粒上，并且其中所述聚合物在低于所述陶瓷温度的温度下塌陷，在高于Theta温度的温度下膨胀。在微电子封装的运行过程中，使用可逆的热增稠润滑脂使润滑脂泵出和空气扩散最小化，同时在重复的热应力下保持润滑脂的流动性。

13. 发明授权

US07815968B2 Centrifugal method for filing high aspect ratio blind mirco vias powdered materials for circuit formation 有权
标题翻译：离心方法，用于提供高比例盲孔微通道用于电路形成的粉末材料
公开(公告)号：US07815968B2
公开(公告)日：2010-10-19
申请号：US12247894
申请日：2008-10-08
申请人： Gareth Hougham , Leena Paivikki Buchwalter , Stephen L. Buchwalter , Jon Casey , Claudius Feger , Matteo Flotta , Jeffrey D. Gelmore , Kathleen C. Hinge , Anurag Jain , Sung K. Kang , John U. Knickerbocker
发明人： Gareth Hougham , Leena Paivikki Buchwalter , Stephen L. Buchwalter , Jon Casey , Claudius Feger , Matteo Flotta , Jeffrey D. Gelmore , Kathleen C. Hinge , Anurag Jain , Sung K. Kang , John U. Knickerbocker
IPC分类号： B05D3/12
CPC分类号： H05K3/4053 , B05D1/002 , H01L21/486 , H01L21/76898 , H05K2201/09509 , H05K2203/1554
摘要： The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.
摘要翻译：本公开一般涉及半导体，集成电路，特别是但不限于，用于填充高纵横比通孔和沟槽的离心方法，其具有粉末，糊料，材料悬浮液，用作导电，结构支撑或电子部件的保护构件。

14. 发明授权

US07773220B2 Method and system for collecting alignment data from coated chips or wafers 失效
标题翻译：用于从涂覆的芯片或晶片收集对准数据的方法和系统
公开(公告)号：US07773220B2
公开(公告)日：2010-08-10
申请号：US12061196
申请日：2008-04-02
申请人： Claudius Feger , Nancy C. LaBianca , Steven E. Steen
发明人： Claudius Feger , Nancy C. LaBianca , Steven E. Steen
IPC分类号： G01B11/00
CPC分类号： H01L23/544 , H01L24/81 , H01L2223/54426 , H01L2223/54453 , H01L2223/5448 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/73104 , H01L2224/81121 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2224/05599
摘要： A process and system for determining alignment data for partially obscured features on wafers or chips when a wafer or chip is substantially coated by an over bump applied material, e.g. a resin or film, and using that data to align the wafers or chips for subsequent operations such as dicing or joining. Position data for alignment is produced by identifying a location of an at least partially obscured feature by varying the depth of focus upon a work piece to determine an SNR approximating a maximum value from an image captured by optical scanning. An SNR above a threshold value can be employed.
摘要翻译：当晶片或芯片基本上被覆盖的凸起涂覆材料涂覆时，用于确定晶片或芯片上部分模糊特征的对准数据的过程和系统，例如晶片或芯片。树脂或膜，并且使用该数据来对准用于后续操作的晶片或芯片，例如切割或接合。用于对准的位置数据通过通过改变工件上的焦点深度来识别至少部分模糊的特征的位置而产生，以从通过光学扫描捕获的图像确定接近最大值的SNR。可以使用高于阈值的SNR。

15. 发明申请

US20100003786A1 CHIP-LEVEL UNDERFILL PROCESS AND STRUCTURES THEREOF 失效
标题翻译：芯片级底层工艺及其结构
公开(公告)号：US20100003786A1
公开(公告)日：2010-01-07
申请号：US12166286
申请日：2008-07-01
申请人： Claudius Feger , Nancy C. LaBianca
发明人： Claudius Feger , Nancy C. LaBianca
IPC分类号： H01L21/00
CPC分类号： H01L21/563 , H01L23/544 , H01L24/29 , H01L24/75 , H01L24/81 , H01L2223/54426 , H01L2223/5448 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/274 , H01L2224/32225 , H01L2224/73104 , H01L2224/73203 , H01L2224/73204 , H01L2224/81121 , H01L2224/81191 , H01L2224/81801 , H01L2224/83191 , H01L2224/83194 , H01L2224/83856 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1461 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： A process comprises forming a first electrical interconnect structure on a surface of a singulated semiconductor chip having an alignment pattern. The alignment pattern is scanned and stored in a scanning device prior to application of a curable underfill coating to the surface of the singulated semiconductor chip. This is followed by applying a curable underfill coating to the surface of the singulated semiconductor chip to produce a coated semiconductor chip. The process also includes a step of delivering the scanned and stored alignment pattern to an alignment and joining device positioned adjacent to and operatively associated with a substrate having a second electrical interconnect structure alignable to make electrical contact with the first electrical interconnect structure. The coated semiconductor chip is placed in the alignment and joining device so that when the scanned and stored alignment pattern is activated the alignment and joining device positions the coated semiconductor chip so that the first electrical interconnect structure is aligned to make electrical contact with the second electrical interconnect structure. This is followed by activating the alignment and joining device to join the coated semiconductor chip to the substrate so that the first electrical interconnect structure is in electrical contact with the second electrical interconnect structure. In one embodiment, the first electrical interconnect structure is placed on a surface of a semiconductor chip array in a wafer to produce the electrically connectable semiconductor structure which is followed by dicing to produce at least one of the singulated semiconductor chips. Another embodiment comprises aligning the fist and second electrical interconnect structures prior to applying the curable underfill coating.
摘要翻译：一种方法包括在具有对准图案的单片半导体芯片的表面上形成第一电互连结构。在将可固化的底部填充涂层施加到单片半导体芯片的表面之前，对准图案被扫描并存储在扫描装置中。然后将可固化的底部填充涂层施加到单片化半导体芯片的表面以制造涂覆的半导体芯片。该过程还包括将扫描和存储的对准图案递送到与具有可与第一电互连结构电接触的第二电互连结构的基板相邻并且可操作地相关联的对准和接合装置的步骤。涂覆的半导体芯片被放置在对准和接合装置中，使得当扫描和存储的对准图案被激活时，对准和接合装置将涂覆的半导体芯片定位，使得第一电互连结构对准以与第二电气互连结构。然后激活对准和接合装置以将涂覆的半导体芯片连接到基板，使得第一电互连结构与第二电互连结构电接触。在一个实施例中，将第一电互连结构放置在晶片中的半导体芯片阵列的表面上，以产生可电连接的半导体结构，随后进行切割以产生至少一个单片半导体芯片。另一个实施例包括在施加可固化底部填充涂层之前对齐第一和第二电互连结构。

16. 发明申请

US20090102070A1 Alignment Marks on the Edge of Wafers and Methods for Same 审中-公开
标题翻译：晶圆边缘上的对准标记和相同的方法
公开(公告)号：US20090102070A1
公开(公告)日：2009-04-23
申请号：US11876677
申请日：2007-10-22
申请人： Claudius Feger , Nancy LaBianca
发明人： Claudius Feger , Nancy LaBianca
IPC分类号： H01L23/544 , H01L21/78
CPC分类号： H01L23/544 , H01L21/563 , H01L24/29 , H01L2223/54493 , H01L2224/16 , H01L2224/274 , H01L2224/73104 , H01L2224/73203 , H01L2224/83191 , H01L2224/83856 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01076 , H01L2924/01082 , H01L2924/10253 , H01L2924/3512 , H01L2924/00
摘要： A semiconductor wafer having alignment marks a sufficient distance from the outer wafer edge that reference dicing channels and a method for same. A process for dicing WLUF coated wafers into singulated chips using said alignment marks on the outer edge of the wafer.
摘要翻译：具有对准标记与参考切割通道的外晶片边缘足够距离的半导体晶片及其方法。使用晶片外边缘上的对准标记将WLUF涂覆的晶片切割成单个芯片的工艺。

17. 发明授权

US06746053B1 System for preventing parallel marketing of retail items 失效
标题翻译：防止零售商品并行营销的制度
公开(公告)号：US06746053B1
公开(公告)日：2004-06-08
申请号：US09182280
申请日：1998-10-29
申请人： Ali Afzali-Ardakani , Claudius Feger , Marco Martens , Paul Andrew Moskowitz , Alejandro Gabriel Schrott , Charles P. Tresser , Robert Jacob von Gutfeld
发明人： Ali Afzali-Ardakani , Claudius Feger , Marco Martens , Paul Andrew Moskowitz , Alejandro Gabriel Schrott , Charles P. Tresser , Robert Jacob von Gutfeld
IPC分类号： B42D1500
CPC分类号： G09F3/00 , G06K19/06028 , G06Q10/087 , Y10S428/913 , Y10T428/1405 , Y10T428/1467 , Y10T428/24934
摘要： A system and method for detecting parallel marketing of an item, include forming at least one of a coating and a code on the item, interrogating the at least one of the coating and said code, and determining from the interrogating whether the item has been transferred from an authorized merchant to an unauthorized merchant.
摘要翻译：一种用于检测物品的并行营销的系统和方法，包括形成所述物品上的涂层和代码中的至少一个，询问所述涂层和所述代码中的至少一个，并且从询问中确定物品是否已被转移从授权的商家到未经授权的商家。

18. 发明授权

US06730618B2 Low k dielectric materials with inherent copper ion migration barrier 失效
标题翻译：具有固有铜离子迁移屏障的低k电介质材料
公开(公告)号：US06730618B2
公开(公告)日：2004-05-04
申请号：US10137009
申请日：2002-05-01
申请人： Stephan Alan Cohen , Claudius Feger , Jeffrey Curtis Hedrick , Jane Margaret Shaw
发明人： Stephan Alan Cohen , Claudius Feger , Jeffrey Curtis Hedrick , Jane Margaret Shaw
IPC分类号： H01L2131
CPC分类号： H01L21/02118 , H01L21/02115 , H01L21/28194 , H01L21/312 , H01L21/3121 , H01L21/3146 , H01L23/53228 , H01L23/5329 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： An interlayer dielectric for preventing Cu ion migration in semiconductor structure containing a Cu region is provided. The interlayer dielectric of the present invention comprises a dielectric material that has a dielectric constant of 3.0 or less and an additive which is highly-capable of binding Cu ions, yet is soluble in the dielectric material. The presence of the additive in the low k dielectric allows for the elimination of conventional inorganic barrier materials such as SiO2 or Si3N4.
摘要翻译：提供了一种用于防止含有Cu区域的半导体结构中的Cu离子迁移的层间电介质。本发明的层间电介质包括介电常数为3.0以下的介电材料和能够结合Cu离子的添加剂，但是其可溶于电介质材料。添加剂在低k电介质中的存在允许消除常规的无机阻挡材料如SiO 2或Si 3 N 4。

19. 发明授权

US6130472A Moisture and ion barrier for protection of devices and interconnect structures 失效
公开(公告)号：US6130472A
公开(公告)日：2000-10-10
申请号：US122353
申请日：1998-07-24
申请人： Claudius Feger , John Patrick Hummel
发明人： Claudius Feger , John Patrick Hummel
IPC分类号： H01L21/60 , H01L21/312 , H01L23/00 , H01L29/40
CPC分类号： H01L23/564 , H01L2924/0002 , H01L2924/09701 , H01L2924/12044
摘要： The present invention provides polymeric materials that can be used as a moisture/ion barrier layer for inhibiting the penetration of moisture and/or ions for coming into contact with the metal wiring found in chip level interconnects. The present invention also provides a means to protect the chip backside from being contaminated by metal atoms or metal ions which are capable of forming mobile silicides, which can migrate to the active sites of the semiconductor and destroy them. The present invention further provides methods of forming such polymeric barrier layers on at least one surface of an interconnect structure.

20. 发明授权

US5619357A Flat panel display containing black matrix polymer 失效
标题翻译：含黑色矩阵聚合物的平板显示器
公开(公告)号：US5619357A
公开(公告)日：1997-04-08
申请号：US466317
申请日：1995-06-06
申请人： Marie Angelopoulos , Ali Afzali-Ardakani , Claudius Feger , Chandrasekhar Narayan
发明人： Marie Angelopoulos , Ali Afzali-Ardakani , Claudius Feger , Chandrasekhar Narayan
IPC分类号： G02F1/1335
CPC分类号： G02F1/133512
摘要： A thin film transistor display that comprises a black matrix polymer layer, comprising a polymer having an optical density of at least about 0.8 per .mu.m and being self-absorbent of visible light and being selected from the group consisting of substituted and unsubstituted polyanilines, substituted and unsubstituted polyparaphenylenevinylenes, substituted and unsubstituted polythiophenes, substituted and unsubstituted polyazines, substituted and unsubstituted polyparaphenylenes, substituted and unsubstituted polyfuranes, substituted and unsubstituted polypyrroles, substituted and unsubstituted polyselenophene, substituted and unsubstituted poly-p-phenylene sulfides and substituted and unsubstituted polyacetylenes, and mixtures thereof, and copolymers thereof. The layer also comprises one or more pigments. The resistivity of the black matrix composite is 10E12 to 10E14 ohm cm.
摘要翻译：一种薄膜晶体管显示器，其包括黑矩阵聚合物层，其包含光密度为至少约0.8每μm的聚合物，并且是可吸收的可见光，并且选自取代和未取代的聚苯胺，取代的取代和未取代的聚噻吩，取代和未取代的聚噻吩，取代和未取代的聚嗪，取代和未取代的聚对苯二烯，取代和未取代的聚呋喃，取代和未取代的聚吡咯，取代和未取代的聚硒吩，取代和未取代的聚对苯硫醚和取代和未取代的聚乙炔，其混合物，及其共聚物。该层还包含一种或多种颜料。黑色矩阵复合材料的电阻率为10E12至10E14欧姆厘米。

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