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11. 发明申请

US20070264776A1 Precision creation of inter-gates insulator 审中-公开
公开(公告)号：US20070264776A1
公开(公告)日：2007-11-15
申请号：US11801301
申请日：2007-05-08
申请人： Zhong Dong , Chuck Jang , Chunchieh Huang
发明人： Zhong Dong , Chuck Jang , Chunchieh Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/511 , H01L29/40114
摘要： An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell. In an alternative embodiment, after the middle, silicon nitride of the ONO structure is defined, another layer of intrinsic silicon is deposited, by way of for example, ALD. Heat and an oxidizing atmosphere are used to convert the second deposited, intrinsic silicon into thermally-grown, silicon dioxide. An ONO structure with two thermally-grown, and spaced apart, silicon oxide layers is thereby provided.

12. 发明申请

US20050124102A1 Substrate isolation in integrated circuits 有权
标题翻译：集成电路中的基板隔离
公开(公告)号：US20050124102A1
公开(公告)日：2005-06-09
申请号：US10732616
申请日：2003-12-09
申请人： Daniel Wang , Chunchieh Huang , Dong Kim
发明人： Daniel Wang , Chunchieh Huang , Dong Kim
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/8247 , H01L27/105 , H01L21/336 , H01L21/76
CPC分类号： H01L27/11526 , H01L21/76237 , H01L21/823481 , H01L27/105 , H01L27/11539 , H01L27/11546
摘要： Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.
摘要翻译：衬底隔离沟槽（224）形成在半导体衬底（120）中。通过离子注入将掺杂剂（例如硼）注入到沟槽侧壁中，以抑制沿着侧壁的电流泄漏。在离子注入期间，晶体管栅极电介质（520）面向离子流，但在随后的热步骤中对栅极电介质的损坏退火。在一些实施例中，掺杂剂注入是成角度的植入物。植入物从晶片的相对侧进行，并且因此从每个有效区域的相对侧进行。每个有源区域包括从一侧注入的区域和从相对侧注入的区域。两个区域重叠以便于阈值电压调整。

13. 发明申请

US20050106793A1 Precision creation of inter-gates insulator 有权
标题翻译：精密创建栅极间绝缘体
公开(公告)号：US20050106793A1
公开(公告)日：2005-05-19
申请号：US10718008
申请日：2003-11-19
申请人： Zhong Dong , Chuck Jang , Chunchieh Huang
发明人： Zhong Dong , Chuck Jang , Chunchieh Huang
IPC分类号： H01L21/28 , H01L29/51 , H01L21/336
CPC分类号： H01L29/511 , H01L21/28273
摘要： An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell. In an alternative embodiment, after the middle, silicon nitride of the ONO structure is defined, another layer of intrinsic silicon is deposited, by way of for example, ALD. Heat and an oxidizing atmosphere are used to convert the second deposited, intrinsic silicon into thermally-grown, silicon dioxide. An ONO structure with two thermally-grown, and spaced apart, silicon oxide layers is thereby provided.
摘要翻译：通过在氧化停止层上沉积本征硅来形成ONO型多晶硅绝缘体。在一个实施方案中，氧化停止层是较低且导电掺杂的多晶硅层的氮化顶表面。在一个实施例中，原子层沉积（ALD）用于精确控制沉积的本征硅的厚度。使用热和氧化气氛将沉积的本征硅转化成热生长的二氧化硅。氧化停止层阻碍更深的氧化。在形成上部和导电掺杂的多晶硅层之前，进一步沉积氮化硅层和另外的氧化硅层以完成ONO结构。在一个实施例中，下部和上部多晶硅层被图案化以分别限定电可重新编程的存储器单元的浮动栅极（FG）和控制栅极（CG）。在替代实施例中，在中间形成ONO结构的氮化硅之后，通过例如ALD沉积另一层本征硅。使用热和氧化气氛将第二沉积的本征硅转化成热生长的二氧化硅。由此提供具有两个热生长和间隔开的氧化硅层的ONO结构。

14. 发明授权

US06657281B1 Bipolar transistor with a low K material in emitter base spacer regions 失效
标题翻译：在发射极基极间隔区域中具有低K材料的双极晶体管
公开(公告)号：US06657281B1
公开(公告)日：2003-12-02
申请号：US09631755
申请日：2000-08-03
申请人： Yih-Feng Chyan , Chunchieh Huang , Chung Wai Leung , Yi Ma , Shahriar Moinian
发明人： Yih-Feng Chyan , Chunchieh Huang , Chung Wai Leung , Yi Ma , Shahriar Moinian
IPC分类号： H01L27082
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0804
摘要： The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the base and in contact with at least a portion of the base, wherein the emitter has a low K layer located therein. The low K layer may be, for example, located proximate a side of the emitter, or it may be located proximate opposing sides of the emitter. In all embodiments, however, the low K layer does not interfere with the proper functioning of the bipolar transistor, and substantially reduces the emitter-base capacitance typically associated with conventional bipolar transistors.
摘要翻译：本发明提供一种位于半导体晶片基板上的双极晶体管。双极晶体管可以包括位于半导体晶片衬底中的集电极，位于集电极中的基极和位于基极上并与基极的至少一部分接触的发射极，其中发射极具有位于其中的低K层。例如，低K层可以位于靠近发射极的一侧，或者它可以位于发射极的相对侧附近。然而，在所有实施例中，低K层不干扰双极晶体管的正常功能，并且基本上减小了通常与常规双极晶体管相关联的发射极 - 基极电容。

15. 发明授权

US07229880B2 Precision creation of inter-gates insulator 有权
标题翻译：精密创建栅极间绝缘体
公开(公告)号：US07229880B2
公开(公告)日：2007-06-12
申请号：US10718008
申请日：2003-11-19
申请人： Zhong Dong , Chuck Jang , Chunchieh Huang
发明人： Zhong Dong , Chuck Jang , Chunchieh Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/511 , H01L21/28273
摘要： An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell. In an alternative embodiment, after the middle, silicon nitride of the ONO structure is defined, another layer of intrinsic silicon is deposited, by way of for example, ALD. Heat and an oxidizing atmosphere are used to convert the second deposited, intrinsic silicon into thermally-grown, silicon dioxide. An ONO structure with two thermally-grown, and spaced apart, silicon oxide layers is thereby provided.
摘要翻译：通过在氧化停止层上沉积本征硅来形成ONO型多晶硅绝缘体。在一个实施方案中，氧化停止层是较低且导电掺杂的多晶硅层的氮化顶表面。在一个实施例中，原子层沉积（ALD）用于精确控制沉积的本征硅的厚度。使用热和氧化气氛将沉积的本征硅转化成热生长的二氧化硅。氧化停止层阻碍更深的氧化。在形成上部和导电掺杂的多晶硅层之前，进一步沉积氮化硅层和另外的氧化硅层以完成ONO结构。在一个实施例中，下部和上部多晶硅层被图案化以分别限定电可重新编程的存储器单元的浮动栅极（FG）和控制栅极（CG）。在替代实施例中，在中间形成ONO结构的氮化硅之后，通过例如ALD沉积另一层本征硅。使用热和氧化气氛将第二沉积的本征硅转化成热生长的二氧化硅。由此提供具有两个热生长和间隔开的氧化硅层的ONO结构。

16. 发明申请

US20050266628A1 Substrate isolation in integrated circuits 有权
公开(公告)号：US20050266628A1
公开(公告)日：2005-12-01
申请号：US11193150
申请日：2005-07-29
申请人： Daniel Wang , Chunchieh Huang , Dong Kim
发明人： Daniel Wang , Chunchieh Huang , Dong Kim
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/8247 , H01L27/105 , H01L21/336
CPC分类号： H01L27/11526 , H01L21/76237 , H01L21/823481 , H01L27/105 , H01L27/11539 , H01L27/11546
摘要： Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

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