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11. 发明授权

US07348804B2 Low leakage and data retention circuitry 有权
标题翻译：低泄漏和数据保持电路
公开(公告)号：US07348804B2
公开(公告)日：2008-03-25
申请号：US11732181
申请日：2007-04-02
申请人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
发明人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
IPC分类号： H03K19/0175
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/144 , G11C5/148 , H02M3/07 , H03K3/0372 , H03K3/356086 , H03K3/356113 , H03K5/14 , H03K17/102 , H03K19/00315
摘要： An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
摘要翻译：集成电路包括第一电路和睡眠晶体管电路。第一个电路接收输入信号并处理输入信号。第一电路还保持具有低泄漏的睡眠状态的数据。睡眠晶体管电路耦合到第一电路并且接收具有负电压的睡眠信号。休眠电路降低处于休眠状态的第一电路的功耗，以便在将数据保留在第一电路中的同时基于睡眠信号具有低泄漏。

12. 发明授权

US07227383B2 Low leakage and data retention circuitry 有权
公开(公告)号：US07227383B2
公开(公告)日：2007-06-05
申请号：US11041687
申请日：2005-01-20
申请人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
发明人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
IPC分类号： H03K19/00
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/144 , G11C5/148 , H02M3/07 , H03K3/0372 , H03K3/356086 , H03K3/356113 , H03K5/14 , H03K17/102 , H03K19/00315
摘要： An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

13. 发明授权

US4642797A High speed first-in-first-out memory 失效
标题翻译：高速先进先出存储器
公开(公告)号：US4642797A
公开(公告)日：1987-02-10
申请号：US551735
申请日：1983-11-10
申请人： Barry A. Hoberman
发明人： Barry A. Hoberman
IPC分类号： G06F5/06 , G06F5/16 , G11C7/00 , G11C13/00
CPC分类号： G06F5/16
摘要： A high speed M-stack fall-through FIFO memory system is disclosed which reduces fall-through delay and which permits at least a doubling of the maximum shift rates at input and output ports. Input port data may be entered in one of M physical memory locations and output port data may be read from one of M physical memory locations.
摘要翻译：公开了一种高速M堆栈落下FIFO存储器系统，其降低了落差延迟，并且允许在输入和输出端口处的最大偏移速率的至少加倍。输入端口数据可以输入到M个物理存储器位置之一中，并且输出端口数据可以从M个物理存储器位置中的一个读取。

14. 发明申请

US20130027125A1 LOW LEAKAGE AND DATA RETENTION CIRCUITRY 有权
标题翻译：低泄漏和数据保持电路
公开(公告)号：US20130027125A1
公开(公告)日：2013-01-31
申请号：US13569613
申请日：2012-08-08
申请人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
发明人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
IPC分类号： G05F1/10
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/144 , G11C5/148 , H02M3/07 , H03K3/0372 , H03K3/356086 , H03K3/356113 , H03K5/14 , H03K17/102 , H03K19/00315
摘要： An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
摘要翻译：集成电路包括第一电路和睡眠晶体管电路。第一个电路接收输入信号并处理输入信号。第一电路还保持具有低泄漏的睡眠状态的数据。睡眠晶体管电路耦合到第一电路并且接收具有负电压的睡眠信号。休眠电路降低处于休眠状态的第一电路的功率消耗，以便在将数据保留在第一电路中的同时基于睡眠信号具有低泄漏。

15. 发明授权

US08253438B2 Low leakage and data retention circuitry 有权
标题翻译：低泄漏和数据保持电路
公开(公告)号：US08253438B2
公开(公告)日：2012-08-28
申请号：US13074291
申请日：2011-03-29
申请人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
发明人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
IPC分类号： H03K17/16
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/144 , G11C5/148 , H02M3/07 , H03K3/0372 , H03K3/356086 , H03K3/356113 , H03K5/14 , H03K17/102 , H03K19/00315
摘要： An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
摘要翻译：集成电路包括第一电路和睡眠晶体管电路。第一个电路接收输入信号并处理输入信号。第一电路还保持具有低泄漏的睡眠状态的数据。睡眠晶体管电路耦合到第一电路并且接收具有负电压的睡眠信号。休眠电路降低处于休眠状态的第一电路的功耗，以便在将数据保留在第一电路中的同时基于睡眠信号具有低泄漏。

16. 发明申请

US20090027080A1 Low leakage and data retention circuitry 有权
公开(公告)号：US20090027080A1
公开(公告)日：2009-01-29
申请号：US12284311
申请日：2008-09-19
申请人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
发明人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
IPC分类号： H03K19/173 , H03K19/0175
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/144 , G11C5/148 , H02M3/07 , H03K3/0372 , H03K3/356086 , H03K3/356113 , H03K5/14 , H03K17/102 , H03K19/00315
摘要： An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

17. 发明授权

US5490257A RAM based FIFO memory half-full detection apparatus and method 失效
标题翻译：基于RAM的FIFO存储器半全检测装置和方法
公开(公告)号：US5490257A
公开(公告)日：1996-02-06
申请号：US840024
申请日：1992-02-24
申请人： Barry A. Hoberman , Stuart T. Auvinen , Patrick Wang , David Wang
发明人： Barry A. Hoberman , Stuart T. Auvinen , Patrick Wang , David Wang
IPC分类号： G06F5/10 , G06F5/12 , G06F12/00 , G11C8/00
CPC分类号： G06F5/12 , G06F2205/126
摘要： A method for detecting a half-full condition of a first-in, first-out memory array. The method of the invention includes the steps of a) moving a write pointer through the array to write data to alternating rows of the memory array; b) moving a read pointer through the array to read data from the alternating rows of the memory array in first-in, first-out order; and c) providing a half-full indication when the read pointer and the write pointer point to adjacent rows in the memory array. This method eliminates the need to route lines across the array to detect a half-full condition, thereby reducing die and power requirements and offering an increase in speed.
摘要翻译：一种用于检测先进先出存储器阵列的半满状态的方法。本发明的方法包括以下步骤：a）通过阵列移动写指针以将数据写入存储器阵列的交替行; b）通过数组移动读指针以先进先出的顺序从存储器阵列的交替行中读取数据; 以及c）当读指针和写指针指向存储器阵列中的相邻行时，提供半满指示。该方法无需在阵列上布线以检测半满状态，从而减少芯片和电源的需求并提高速度。

18. 发明授权

US4954987A Interleaved sensing system for FIFO and burst-mode memories 失效
标题翻译：用于FIFO和突发模式存储器的交错感测系统
公开(公告)号：US4954987A
公开(公告)日：1990-09-04
申请号：US380368
申请日：1989-07-17
申请人： Stuart T. Auvinen , Barry A. Hoberman
发明人： Stuart T. Auvinen , Barry A. Hoberman
IPC分类号： G11C11/401 , G06F5/00 , G11C7/10 , G11C11/409 , G11C11/419
CPC分类号： G11C11/419 , G11C7/1021 , G11C7/1048 , G06F5/00
摘要： An interleaved sensing system for decreasing the read access time in a sequential memory includes a sequential memory array formed of a plurality of memory cells for storing data. The memory cells are arranged in a plurality of odd columns and a plurality of even columns. Sensing means are provided for interleaving the stored data in the memory cells in the odd columns with the stored data in the memory cells in the even columns. An output buffer is coupled to the sensing means for generating data output representing alternately the stored data in the odd and even columns during alternate read cycles.

19. 发明授权

US4862419A High speed pointer based first-in-first-out memory 失效
标题翻译：基于高速指针的先进先出存储器
公开(公告)号：US4862419A
公开(公告)日：1989-08-29
申请号：US908059
申请日：1986-09-16
申请人： Barry A. Hoberman
发明人： Barry A. Hoberman
IPC分类号： G06F5/10 , G06F5/16 , G11C7/00
CPC分类号： G06F5/16
摘要： A FIFO memory system organizes a memory with N word storage locations into M pointer-based random access memories, each containing N/M storage locations. A sequence of data words is written into and read out of the M RAMs in a cyclical fashion. An M fold increase in write rate is obtained by an input control logic which causes all M RAMs to be in a different stage of the shift-in cycle at the same time. Similarly, an M fold increase in read rate is obtained by an output control logic which causes all M RAMs to be simultaneously in a different stage of the shift-out cycle. The output signals of the RAMs being read are multiplexed to generate the original sequence.
摘要翻译： FIFO存储器系统将具有N个字存储位置的存储器组织到基于M个指针的随机存取存储器中，每个存储单元包含N / M个存储位置。数据字序列以循环方式写入并读出M RAM。通过输入控制逻辑获得写入速率的M倍增加，其使得所有M RAM同时处于移入周期的不同阶段。类似地，通过输出控制逻辑获得读取速率的M倍增加，其使所有M RAM同时处于移出周期的不同阶段。正在读取的RAM的输出信号被多路复用以产生原始序列。

20. 发明授权

US4802122A Fast flush for a first-in first-out memory 失效
标题翻译：快速刷新先进先出的内存
公开(公告)号：US4802122A
公开(公告)日：1989-01-31
申请号：US043521
申请日：1987-04-28
申请人： Stuart T. Auvinen , Barry A. Hoberman
发明人： Stuart T. Auvinen , Barry A. Hoberman
IPC分类号： G11C11/41 , G06F5/10 , G11C8/16 , G11C11/00
CPC分类号： G06F5/10 , G11C7/12 , G11C8/16
摘要： In a memory circuit including a write bit-line for writing data into a memory cell, and a read bit-line for reading data from the cell, a transistor is included, connected with the write bit-line and the read bit-line, so that when a fast flush signal is applied to the gate of that transistor, direct connection is made between the write bit-line and read bit-line, so that data is written into the cell, but can be read simultaneously from the read bit-line, reducing the fall-through delay.

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